Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * SBI initialilization and all extension implementation. |
| 4 | * |
| 5 | * Copyright (c) 2020 Western Digital Corporation or its affiliates. |
| 6 | * |
| 7 | * Taken from Linux arch/riscv/kernel/sbi.c |
| 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <asm/encoding.h> |
| 12 | #include <asm/sbi.h> |
| 13 | |
| 14 | /* default SBI version is 0.1 */ |
| 15 | unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; |
| 16 | |
| 17 | struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, |
| 18 | unsigned long arg1, unsigned long arg2, |
| 19 | unsigned long arg3, unsigned long arg4, |
| 20 | unsigned long arg5) |
| 21 | { |
| 22 | struct sbiret ret; |
| 23 | |
| 24 | register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); |
| 25 | register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); |
| 26 | register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); |
| 27 | register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); |
| 28 | register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4); |
| 29 | register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5); |
| 30 | register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); |
| 31 | register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); |
| 32 | asm volatile ("ecall" |
| 33 | : "+r" (a0), "+r" (a1) |
| 34 | : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) |
| 35 | : "memory"); |
| 36 | ret.error = a0; |
| 37 | ret.value = a1; |
| 38 | |
| 39 | return ret; |
| 40 | } |
| 41 | |
Atish Patra | a7edd07 | 2020-04-21 14:51:57 -0700 | [diff] [blame] | 42 | /** |
| 43 | * sbi_set_timer() - Program the timer for next timer event. |
| 44 | * @stime_value: The value after which next timer event should fire. |
| 45 | * |
| 46 | * Return: None |
| 47 | */ |
| 48 | void sbi_set_timer(uint64_t stime_value) |
| 49 | { |
| 50 | #if __riscv_xlen == 32 |
| 51 | sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value, |
| 52 | stime_value >> 32, 0, 0, 0, 0); |
| 53 | #else |
| 54 | sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value, |
| 55 | 0, 0, 0, 0, 0); |
| 56 | #endif |
| 57 | } |
| 58 | |
Bin Meng | 887d809 | 2020-03-09 19:35:30 -0700 | [diff] [blame] | 59 | #ifdef CONFIG_SBI_V01 |
| 60 | |
Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 61 | /** |
| 62 | * sbi_console_putchar() - Writes given character to the console device. |
| 63 | * @ch: The data to be written to the console. |
| 64 | * |
| 65 | * Return: None |
| 66 | */ |
| 67 | void sbi_console_putchar(int ch) |
| 68 | { |
| 69 | sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); |
| 70 | } |
| 71 | |
| 72 | /** |
| 73 | * sbi_console_getchar() - Reads a byte from console device. |
| 74 | * |
| 75 | * Returns the value read from console. |
| 76 | */ |
| 77 | int sbi_console_getchar(void) |
| 78 | { |
| 79 | struct sbiret ret; |
| 80 | |
| 81 | ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0); |
| 82 | |
| 83 | return ret.error; |
| 84 | } |
| 85 | |
| 86 | /** |
| 87 | * sbi_clear_ipi() - Clear any pending IPIs for the calling hart. |
| 88 | * |
| 89 | * Return: None |
| 90 | */ |
| 91 | void sbi_clear_ipi(void) |
| 92 | { |
| 93 | sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); |
| 94 | } |
| 95 | |
| 96 | /** |
| 97 | * sbi_shutdown() - Remove all the harts from executing supervisor code. |
| 98 | * |
| 99 | * Return: None |
| 100 | */ |
| 101 | void sbi_shutdown(void) |
| 102 | { |
| 103 | sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); |
| 104 | } |
| 105 | |
Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 106 | /** |
| 107 | * sbi_send_ipi() - Send an IPI to any hart. |
| 108 | * @hart_mask: A cpu mask containing all the target harts. |
| 109 | * |
| 110 | * Return: None |
| 111 | */ |
| 112 | void sbi_send_ipi(const unsigned long *hart_mask) |
| 113 | { |
Bin Meng | f7e6d33 | 2020-03-09 19:35:31 -0700 | [diff] [blame] | 114 | sbi_ecall(SBI_EXT_SEND_IPI, SBI_FID_SEND_IPI, (unsigned long)hart_mask, |
Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 115 | 0, 0, 0, 0, 0); |
| 116 | } |
| 117 | |
| 118 | /** |
| 119 | * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts. |
| 120 | * @hart_mask: A cpu mask containing all the target harts. |
| 121 | * |
| 122 | * Return: None |
| 123 | */ |
| 124 | void sbi_remote_fence_i(const unsigned long *hart_mask) |
| 125 | { |
Bin Meng | f7e6d33 | 2020-03-09 19:35:31 -0700 | [diff] [blame] | 126 | sbi_ecall(SBI_EXT_REMOTE_FENCE_I, SBI_FID_REMOTE_FENCE_I, |
| 127 | (unsigned long)hart_mask, 0, 0, 0, 0, 0); |
Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | /** |
| 131 | * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote |
| 132 | * harts for the specified virtual address range. |
| 133 | * @hart_mask: A cpu mask containing all the target harts. |
| 134 | * @start: Start of the virtual address |
| 135 | * @size: Total size of the virtual address range. |
| 136 | * |
| 137 | * Return: None |
| 138 | */ |
| 139 | void sbi_remote_sfence_vma(const unsigned long *hart_mask, |
| 140 | unsigned long start, |
| 141 | unsigned long size) |
| 142 | { |
Bin Meng | f7e6d33 | 2020-03-09 19:35:31 -0700 | [diff] [blame] | 143 | sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA, SBI_FID_REMOTE_SFENCE_VMA, |
Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 144 | (unsigned long)hart_mask, start, size, 0, 0, 0); |
| 145 | } |
| 146 | |
| 147 | /** |
| 148 | * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given |
| 149 | * remote harts for a virtual address range belonging to a specific ASID. |
| 150 | * |
| 151 | * @hart_mask: A cpu mask containing all the target harts. |
| 152 | * @start: Start of the virtual address |
| 153 | * @size: Total size of the virtual address range. |
| 154 | * @asid: The value of address space identifier (ASID). |
| 155 | * |
| 156 | * Return: None |
| 157 | */ |
| 158 | void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, |
| 159 | unsigned long start, |
| 160 | unsigned long size, |
| 161 | unsigned long asid) |
| 162 | { |
Bin Meng | f7e6d33 | 2020-03-09 19:35:31 -0700 | [diff] [blame] | 163 | sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA_ASID, |
| 164 | SBI_FID_REMOTE_SFENCE_VMA_ASID, |
Bin Meng | ee3bcd0 | 2020-03-09 19:35:28 -0700 | [diff] [blame] | 165 | (unsigned long)hart_mask, start, size, asid, 0, 0); |
| 166 | } |
| 167 | |
| 168 | /** |
| 169 | * sbi_probe_extension() - Check if an SBI extension ID is supported or not. |
| 170 | * @extid: The extension ID to be probed. |
| 171 | * |
| 172 | * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise. |
| 173 | */ |
| 174 | int sbi_probe_extension(int extid) |
| 175 | { |
| 176 | struct sbiret ret; |
| 177 | |
| 178 | ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, |
| 179 | 0, 0, 0, 0, 0); |
| 180 | if (!ret.error) |
| 181 | if (ret.value) |
| 182 | return ret.value; |
| 183 | |
| 184 | return -ENOTSUPP; |
| 185 | } |
Atish Patra | a7edd07 | 2020-04-21 14:51:57 -0700 | [diff] [blame] | 186 | #endif /* CONFIG_SBI_V01 */ |