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git01.mediatek.com / filogic / uboot / 2510a815bf164897dffa70c347c7a0a0d047cbdb / . / arch / arm / include / asm / arch-lpc32xx / config.h
blob: 22f39cad5916b6d7f055459904f211fc7db14027 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]2/*
3 * Common definitions for LPC32XX board configurations
4 *
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]6 */
7
8#ifndef _LPC32XX_CONFIG_H
9#define _LPC32XX_CONFIG_H
10
Vladimir Zapolskiydb6a14f2015-02-12 00:24:20 +0200[diff] [blame]11
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]12/* Basic CPU architecture */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]13
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]14/* UART configuration */
Trevor Woerner0b881ac2021-06-10 22:37:02 -0400[diff] [blame]15#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
16 (CONFIG_CONS_INDEX == 7)
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]17#if !defined(CONFIG_LPC32XX_HSUART)
18#define CONFIG_LPC32XX_HSUART
19#endif
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]20#endif
21
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]22#if !defined(CONFIG_SYS_NS16550_CLK)
23#define CONFIG_SYS_NS16550_CLK 13000000
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]24#endif
Vladimir Zapolskiy8bf94502015-12-19 23:29:25 +0200[diff] [blame]25
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]26#define CONFIG_SYS_BAUDRATE_TABLE \
27 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
28
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +0200[diff] [blame]29/* Ethernet */
30#define LPC32XX_ETH_BASE ETHERNET_BASE
31
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]32/* NAND */
33#if defined(CONFIG_NAND_LPC32XX_SLC)
34#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
35#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
36
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]37#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]38#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
39 48, 49, 50, 51, 52, 53, 54, 55, \
40 56, 57, 58, 59, 60, 61, 62, 63, }
41#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
42#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]43#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
44#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
45#else
46#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
47#endif
48
49#define CONFIG_SYS_NAND_ECCSIZE 0x100
50#define CONFIG_SYS_NAND_ECCBYTES 3
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300[diff] [blame]51#endif /* CONFIG_NAND_LPC32XX_SLC */
52
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]53/* NOR Flash */
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]54
Vladimir Zapolskiy69ec0752015-08-12 20:32:08 +0300[diff] [blame]55/* USB OHCI */
56#if defined(CONFIG_USB_OHCI_LPC32XX)
57#define CONFIG_USB_OHCI_NEW
58#define CONFIG_SYS_USB_OHCI_CPU_INIT
59#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
60#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
61#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
62#endif
63
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +0000[diff] [blame]64#endif /* _LPC32XX_CONFIG_H */