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git01.mediatek.com / filogic / uboot / 24fbe6ba9c33d7d7c57c8370cfc886077ab520e6 / . / include / configs / at91sam9261ek.h
blob: fb4695c1abf504853268eaa5e46969bf39a7450e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]2/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +0100[diff] [blame]4 * Stelian Pop <stelian@popies.net>
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9261EK board.
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* ARM asynchronous clock */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]14#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich443873d2010-02-24 10:29:16 +0100[diff] [blame]15#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]16
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]17#ifdef CONFIG_AT91SAM9G10
18#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200[diff] [blame]19#else
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]20#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200[diff] [blame]21#endif
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]22
23#include <asm/hardware.h>
24
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]25#define CONFIG_ATMEL_LEGACY
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]26
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]27/*
28 * Hardware drivers
29 */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]30
Stelian Pop905ed222008-05-08 14:52:30 +0200[diff] [blame]31/* LCD */
Stelian Pop905ed222008-05-08 14:52:30 +0200[diff] [blame]32#define LCD_BPP LCD_COLOR8
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]33#define CONFIG_LCD_LOGO
Stelian Pop905ed222008-05-08 14:52:30 +0200[diff] [blame]34#undef LCD_TEST_PATTERN
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]35#define CONFIG_LCD_INFO
36#define CONFIG_LCD_INFO_BELOW_LOGO
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]37#define CONFIG_ATMEL_LCD
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200[diff] [blame]38#ifdef CONFIG_AT91SAM9261EK
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]39#define CONFIG_ATMEL_LCD_BGR555
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200[diff] [blame]40#endif
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]41
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]42/*
43 * BOOTP options
44 */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]45#define CONFIG_BOOTP_BOOTFILESIZE
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]46
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]47/* SDRAM */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]48#define CONFIG_SYS_SDRAM_BASE 0x20000000
49#define CONFIG_SYS_SDRAM_SIZE 0x04000000
50#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou.Yang@microchip.comb59fe682017-07-21 13:28:40 +0800[diff] [blame]51 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]52
53/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]54#ifdef CONFIG_CMD_NAND
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]55#define CONFIG_SYS_MAX_NAND_DEVICE 1
56#define CONFIG_SYS_NAND_BASE 0x40000000
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]57#define CONFIG_SYS_NAND_DBW_8
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]58/* our ALE is AD22 */
59#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
60/* our CLE is AD21 */
61#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
62#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
63#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
Wolfgang Denk1f797742009-07-18 21:52:24 +0200[diff] [blame]64
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]65#endif
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]66
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]67/* Ethernet */
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]68#define CONFIG_DRIVER_DM9000
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]69#define CONFIG_DM9000_BASE 0x30000000
70#define DM9000_IO CONFIG_DM9000_BASE
71#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]72#define CONFIG_DM9000_USE_16BIT
73#define CONFIG_DM9000_NO_SROM
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]74#define CONFIG_NET_RETRY_COUNT 20
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]75#define CONFIG_RESET_PHY_R
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]76
77/* USB */
Jean-Christophe PLAGNIOL-VILLARDd42643f2009-03-27 23:26:44 +0100[diff] [blame]78#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800[diff] [blame]79#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]80#define CONFIG_USB_OHCI_NEW
Xu, Hong0a614942011-07-31 22:49:00 +0000[diff] [blame]81#define CONFIG_SYS_USB_OHCI_CPU_INIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]82#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200[diff] [blame]83#ifdef CONFIG_AT91SAM9G10EK
84#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
85#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]86#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200[diff] [blame]87#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]88#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]89
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]90#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]91
92/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Wenyou.Yang@microchip.comb59fe682017-07-21 13:28:40 +0800[diff] [blame]93#define CONFIG_BOOTCOMMAND "sf probe 0; " \
94 "sf read 0x22000000 0x84000 0x294000; " \
95 "bootm 0x22000000"
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]96
Nicolas Ferre09e10902008-12-06 13:11:14 +0100[diff] [blame]97#elif CONFIG_SYS_USE_DATAFLASH_CS3
98
99/* bootstrap + u-boot + env + linux in dataflash on CS3 */
Wenyou.Yang@microchip.comb59fe682017-07-21 13:28:40 +0800[diff] [blame]100#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \
101 "sf read 0x22000000 0x84000 0x294000; " \
102 "bootm 0x22000000"
Nicolas Ferre09e10902008-12-06 13:11:14 +0100[diff] [blame]103
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]104#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]105
106/* bootstrap + u-boot + env + linux in nandflash */
Bo Shena8fd0632013-02-20 00:16:25 +0000[diff] [blame]107#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]108#endif
109
Stelian Pop61e69d72008-05-08 20:52:22 +0200[diff] [blame]110#endif