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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Graeme Russa875dda2011-12-23 16:51:29 +11002/*
3 * (C) Copyright 2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russa875dda2011-12-23 16:51:29 +11005 */
Bin Meng535109a2015-08-13 00:29:10 -07006
Graeme Russa875dda2011-12-23 16:51:29 +11007#include <common.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090010#include <linux/errno.h>
Simon Glass004ba172015-01-01 16:18:11 -070011#include <asm/mtrr.h>
Graeme Russa875dda2011-12-23 16:51:29 +110012
13DECLARE_GLOBAL_DATA_PTR;
14
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110015int init_cache_f_r(void)
16{
Simon Glassa72a7ab2019-09-25 08:56:49 -060017 bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
18 IS_ENABLED(CONFIG_FSP_VERSION2);
Simon Glass004ba172015-01-01 16:18:11 -070019 int ret;
20
Simon Glass619af332021-03-15 18:00:34 +130021 if (!ll_boot_init())
22 return 0;
23
Simon Glassa72a7ab2019-09-25 08:56:49 -060024 do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
25 !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
26
27 if (do_mtrr) {
28 ret = mtrr_commit(false);
29 /*
30 * If MTRR MSR is not implemented by the processor, just ignore
31 * it
32 */
33 if (ret && ret != -ENOSYS)
34 return ret;
35 }
36
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110037 /* Initialise the CPU cache(s) */
38 return init_cache();
39}