Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 1 | /* |
Enric Balletbo i Serra | aca204b | 2013-07-25 09:27:38 +0200 | [diff] [blame] | 2 | * Board functions for IGEP COM AQUILA based boards |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <errno.h> |
| 11 | #include <spl.h> |
| 12 | #include <asm/arch/cpu.h> |
| 13 | #include <asm/arch/hardware.h> |
| 14 | #include <asm/arch/omap.h> |
| 15 | #include <asm/arch/ddr_defs.h> |
| 16 | #include <asm/arch/clock.h> |
| 17 | #include <asm/arch/gpio.h> |
| 18 | #include <asm/arch/mmc_host_def.h> |
| 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/io.h> |
| 21 | #include <asm/emif.h> |
| 22 | #include <asm/gpio.h> |
| 23 | #include <i2c.h> |
| 24 | #include <miiphy.h> |
| 25 | #include <cpsw.h> |
| 26 | #include "board.h" |
| 27 | |
| 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 30 | /* MII mode defines */ |
| 31 | #define RMII_MODE_ENABLE 0x4D |
| 32 | |
| 33 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 34 | |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 35 | #ifdef CONFIG_SPL_BUILD |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 36 | static const struct ddr_data ddr3_data = { |
| 37 | .datardsratio0 = K4B2G1646EBIH9_RD_DQS, |
| 38 | .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, |
| 39 | .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, |
| 40 | .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, |
| 41 | .datadldiff0 = PHY_DLL_LOCK_DIFF, |
| 42 | }; |
| 43 | |
| 44 | static const struct cmd_control ddr3_cmd_ctrl_data = { |
| 45 | .cmd0csratio = K4B2G1646EBIH9_RATIO, |
| 46 | .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, |
| 47 | .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, |
| 48 | |
| 49 | .cmd1csratio = K4B2G1646EBIH9_RATIO, |
| 50 | .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, |
| 51 | .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, |
| 52 | |
| 53 | .cmd2csratio = K4B2G1646EBIH9_RATIO, |
| 54 | .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, |
| 55 | .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, |
| 56 | }; |
| 57 | |
| 58 | static struct emif_regs ddr3_emif_reg_data = { |
| 59 | .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG, |
| 60 | .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF, |
| 61 | .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1, |
| 62 | .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2, |
| 63 | .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3, |
| 64 | .zq_config = K4B2G1646EBIH9_ZQ_CFG, |
| 65 | .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, |
| 66 | }; |
Lokesh Vutla | 89a83bf | 2013-07-30 10:48:52 +0530 | [diff] [blame] | 67 | |
| 68 | #define OSC (V_OSCK/1000000) |
| 69 | const struct dpll_params dpll_ddr = { |
| 70 | 303, OSC-1, 1, -1, -1, -1, -1}; |
| 71 | |
| 72 | const struct dpll_params *get_dpll_ddr_params(void) |
| 73 | { |
| 74 | return &dpll_ddr; |
| 75 | } |
| 76 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 77 | void set_uart_mux_conf(void) |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 78 | { |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 79 | enable_uart0_pin_mux(); |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 80 | } |
Lokesh Vutla | b1b6fba | 2013-07-30 10:48:53 +0530 | [diff] [blame] | 81 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 82 | void set_mux_conf_regs(void) |
| 83 | { |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 84 | enable_board_pin_mux(); |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 85 | } |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 86 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 87 | void sdram_init(void) |
| 88 | { |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 89 | config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, |
| 90 | &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 91 | } |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 92 | #endif |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * Basic board specific setup. Pinmux has been handled already. |
| 96 | */ |
| 97 | int board_init(void) |
| 98 | { |
Tom Rini | f3b6a1d | 2013-08-09 11:22:13 -0400 | [diff] [blame] | 99 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
Enric Balletbo i Serra | 9b96f46 | 2013-04-04 22:27:58 +0000 | [diff] [blame] | 100 | |
| 101 | gpmc_init(); |
| 102 | |
| 103 | return 0; |
| 104 | } |
| 105 | |
| 106 | #if defined(CONFIG_DRIVER_TI_CPSW) |
| 107 | static void cpsw_control(int enabled) |
| 108 | { |
| 109 | /* VTP can be added here */ |
| 110 | |
| 111 | return; |
| 112 | } |
| 113 | |
| 114 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 115 | { |
| 116 | .slave_reg_ofs = 0x208, |
| 117 | .sliver_reg_ofs = 0xd80, |
| 118 | .phy_id = 0, |
| 119 | .phy_if = PHY_INTERFACE_MODE_RMII, |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static struct cpsw_platform_data cpsw_data = { |
| 124 | .mdio_base = CPSW_MDIO_BASE, |
| 125 | .cpsw_base = CPSW_BASE, |
| 126 | .mdio_div = 0xff, |
| 127 | .channels = 8, |
| 128 | .cpdma_reg_ofs = 0x800, |
| 129 | .slaves = 1, |
| 130 | .slave_data = cpsw_slaves, |
| 131 | .ale_reg_ofs = 0xd00, |
| 132 | .ale_entries = 1024, |
| 133 | .host_port_reg_ofs = 0x108, |
| 134 | .hw_stats_reg_ofs = 0x900, |
| 135 | .mac_control = (1 << 5), |
| 136 | .control = cpsw_control, |
| 137 | .host_port_num = 0, |
| 138 | .version = CPSW_CTRL_VERSION_2, |
| 139 | }; |
| 140 | |
| 141 | int board_eth_init(bd_t *bis) |
| 142 | { |
| 143 | int rv, ret = 0; |
| 144 | uint8_t mac_addr[6]; |
| 145 | uint32_t mac_hi, mac_lo; |
| 146 | |
| 147 | if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { |
| 148 | /* try reading mac address from efuse */ |
| 149 | mac_lo = readl(&cdev->macid0l); |
| 150 | mac_hi = readl(&cdev->macid0h); |
| 151 | mac_addr[0] = mac_hi & 0xFF; |
| 152 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 153 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 154 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 155 | mac_addr[4] = mac_lo & 0xFF; |
| 156 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 157 | if (is_valid_ether_addr(mac_addr)) |
| 158 | eth_setenv_enetaddr("ethaddr", mac_addr); |
| 159 | } |
| 160 | |
| 161 | writel(RMII_MODE_ENABLE, &cdev->miisel); |
| 162 | |
| 163 | rv = cpsw_register(&cpsw_data); |
| 164 | if (rv < 0) |
| 165 | printf("Error %d registering CPSW switch\n", rv); |
| 166 | else |
| 167 | ret += rv; |
| 168 | |
| 169 | return ret; |
| 170 | } |
| 171 | #endif |
| 172 | |