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git01.mediatek.com / filogic / uboot / 23529df1f5743e5ca61b1818d3663c4e709daa6a / . / board / Marvell / sheevaplug / sheevaplug.c
blob: 6c6106c23c55762c5c814a032535671919bcbb19 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]2/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]6 */
7
8#include <common.h>
9#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]10#include <net.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -0600[diff] [blame]11#include <asm/mach-types.h>
Lei Wen298ae912011-10-18 20:11:42 +0530[diff] [blame]12#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]13#include <asm/arch/soc.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]14#include <asm/arch/mpp.h>
15#include "sheevaplug.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]19int board_early_init_f(void)
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]20{
21 /*
22 * default gpio configuration
23 * There are maximum 64 gpios controlled through 2 sets of registers
24 * the below configuration configures mainly initial LED status
25 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]26 mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
27 SHEEVAPLUG_OE_VAL_HIGH,
28 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]29
30 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]31 static const u32 kwmpp_config[] = {
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]32 MPP0_NF_IO2,
33 MPP1_NF_IO3,
34 MPP2_NF_IO4,
35 MPP3_NF_IO5,
36 MPP4_NF_IO6,
37 MPP5_NF_IO7,
38 MPP6_SYSRST_OUTn,
39 MPP7_GPO,
40 MPP8_UART0_RTS,
41 MPP9_UART0_CTS,
42 MPP10_UART0_TXD,
43 MPP11_UART0_RXD,
44 MPP12_SD_CLK,
45 MPP13_SD_CMD,
46 MPP14_SD_D0,
47 MPP15_SD_D1,
48 MPP16_SD_D2,
49 MPP17_SD_D3,
50 MPP18_NF_IO0,
51 MPP19_NF_IO1,
52 MPP20_GPIO,
53 MPP21_GPIO,
54 MPP22_GPIO,
55 MPP23_GPIO,
56 MPP24_GPIO,
57 MPP25_GPIO,
58 MPP26_GPIO,
59 MPP27_GPIO,
60 MPP28_GPIO,
61 MPP29_TSMP9,
62 MPP30_GPIO,
63 MPP31_GPIO,
64 MPP32_GPIO,
65 MPP33_GPIO,
66 MPP34_GPIO,
67 MPP35_GPIO,
68 MPP36_GPIO,
69 MPP37_GPIO,
70 MPP38_GPIO,
71 MPP39_GPIO,
72 MPP40_GPIO,
73 MPP41_GPIO,
74 MPP42_GPIO,
75 MPP43_GPIO,
76 MPP44_GPIO,
77 MPP45_GPIO,
78 MPP46_GPIO,
79 MPP47_GPIO,
80 MPP48_GPIO,
81 MPP49_GPIO,
82 0
83 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]84 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]85 return 0;
86}
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]87
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530[diff] [blame]88int board_init(void)
89{
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]90 /*
91 * arch number of board
92 */
93 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
94
95 /* adress of boot parameters */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]96 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]97
98 return 0;
99}
100
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530[diff] [blame]101#ifdef CONFIG_RESET_PHY_R
102/* Configure and enable MV88E1116 PHY */
103void reset_phy(void)
104{
105 u16 reg;
106 u16 devadr;
107 char *name = "egiga0";
108
109 if (miiphy_set_current_dev(name))
110 return;
111
112 /* command to read PHY dev address */
113 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
114 printf("Err..%s could not read PHY dev address\n",
115 __FUNCTION__);
116 return;
117 }
118
119 /*
120 * Enable RGMII delay on Tx and Rx for CPU port
121 * Ref: sec 4.7.2 of chip datasheet
122 */
123 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
124 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
125 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
126 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
127 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
128
129 /* reset the phy */
130 miiphy_reset(name, devadr);
131
132 printf("88E1116 Initialized on %s\n", name);
133}
134#endif /* CONFIG_RESET_PHY_R */