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git01.mediatek.com / filogic / uboot / 231d2ba5804c82cf2467a6658bb7d3eb8ade634c / . / board / CZ.NIC / turris_1x / tlb.c
blob: f35a55583850e972ac573fa63d3e5d3aea8add41 [file] [log] [blame]
Pali Rohár6763ff82024-06-06 18:33:26 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2// (C) 2022 Pali Rohár <pali@kernel.org>
3
4#include <config.h>
5#include <mpc85xx.h>
6#include <asm/mmu.h>
7#include <linux/sizes.h>
8#include <linux/build_bug.h>
9
10/*
11 * NOTE: e500v2 supports only following Book-E page sizes:
12 *
13 * TLB0:
14 * BOOKE_PAGESZ_4K
15 *
16 * TLB1:
17 * BOOKE_PAGESZ_4K
18 * BOOKE_PAGESZ_16K
19 * BOOKE_PAGESZ_64K
20 * BOOKE_PAGESZ_256K
21 * BOOKE_PAGESZ_1M
22 * BOOKE_PAGESZ_4M
23 * BOOKE_PAGESZ_16M
24 * BOOKE_PAGESZ_64M
25 * BOOKE_PAGESZ_256M
26 * BOOKE_PAGESZ_1G
27 * BOOKE_PAGESZ_4G
28 */
29
30struct fsl_e_tlb_entry tlb_table[] = {
31 /* TLB 0 */
32
33 /* ***** - Initial stack in L1 cache 16K */
34 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 0 * SZ_4K,
35 CFG_SYS_INIT_RAM_ADDR_PHYS + 0 * SZ_4K,
36 MAS3_SX | MAS3_SW | MAS3_SR, 0,
37 0, 0, BOOKE_PAGESZ_4K, 0),
38 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 1 * SZ_4K,
39 CFG_SYS_INIT_RAM_ADDR_PHYS + 1 * SZ_4K,
40 MAS3_SX | MAS3_SW | MAS3_SR, 0,
41 0, 0, BOOKE_PAGESZ_4K, 0),
42 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 2 * SZ_4K,
43 CFG_SYS_INIT_RAM_ADDR_PHYS + 2 * SZ_4K,
44 MAS3_SX | MAS3_SW | MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
46 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 3 * SZ_4K,
47 CFG_SYS_INIT_RAM_ADDR_PHYS + 3 * SZ_4K,
48 MAS3_SX | MAS3_SW | MAS3_SR, 0,
49 0, 0, BOOKE_PAGESZ_4K, 0),
50
51 /* TLB 1 */
52
53 /* *I*** - Boot page 4K */
54 SET_TLB_ENTRY(1, BPTR_VIRT_ADDR,
55 0xfffff000,
56 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
57 0, 0, BOOKE_PAGESZ_4K, 1),
58
59 /* *I*G* - CCSR 1M */
60 SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR,
61 CFG_SYS_CCSRBAR_PHYS,
62 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
63 0, 1, BOOKE_PAGESZ_1M, 1),
64
65 /* W**G* - NOR 16M */
66 /* This will be changed to *I*G* after relocation to RAM in board_early_init_r() */
67 SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE,
68 CFG_SYS_FLASH_BASE_PHYS,
69 MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
70 0, 2, BOOKE_PAGESZ_16M, 1),
71
72 /* *I*G* - CPLD 256K (effective 128K) */
73 SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE,
74 CFG_SYS_CPLD_BASE_PHYS,
75 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
76 0, 3, BOOKE_PAGESZ_256K, 1),
77
78 /* *I*G* - NAND 256K */
79 SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE,
80 CFG_SYS_NAND_BASE_PHYS,
81 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
82 0, 4, BOOKE_PAGESZ_256K, 1),
83
84 /* *I*G* - PCIe MEM (bus 1 and 2) 1G */
85 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT,
86 CFG_SYS_PCIE1_MEM_PHYS,
87 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
88 0, 5, BOOKE_PAGESZ_1G, 1),
89
90 /* *I*G* - PCIe MEM (bus 3) 4M (effective 2M) */
91 SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT,
92 CFG_SYS_PCIE3_MEM_PHYS,
93 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
94 0, 6, BOOKE_PAGESZ_4M, 1),
95
96 /* *I*G* - PCIe I/O (all 3 buses) 256K (effective 192K) */
97 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT,
98 CFG_SYS_PCIE1_IO_PHYS,
99 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
100 0, 7, BOOKE_PAGESZ_256K, 1),
101
102#ifdef CFG_SYS_INIT_L2_ADDR
103 /* ***G* - Initial SRAM in L2 cache 512K */
104 SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR,
105 CFG_SYS_INIT_L2_ADDR_PHYS,
106 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
107 0, 8, BOOKE_PAGESZ_256K, 1),
108 SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + SZ_256K,
109 CFG_SYS_INIT_L2_ADDR_PHYS + SZ_256K,
110 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
111 0, 9, BOOKE_PAGESZ_256K, 1),
112#endif
113
114#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
115 /* **M** - SDRAM 2G */
116 SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE,
117 CFG_SYS_DDR_SDRAM_BASE,
118 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
119 0, 10, BOOKE_PAGESZ_1G, 1),
120 SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + SZ_1G,
121 CFG_SYS_DDR_SDRAM_BASE + SZ_1G,
122 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
123 0, 11, BOOKE_PAGESZ_1G, 1),
124#endif
125};
126
127int num_tlb_entries = ARRAY_SIZE(tlb_table);
128
129/*
130 * PCIe MEM TLB entry expects that second PCIe MEM window is mapped after the
131 * first PCIe MEM window. Check for this requirement.
132 */
133static_assert(CFG_SYS_PCIE1_MEM_VIRT + SZ_512M == CFG_SYS_PCIE2_MEM_VIRT);
134static_assert(CFG_SYS_PCIE1_MEM_PHYS + SZ_512M == CFG_SYS_PCIE2_MEM_PHYS);
135
136/*
137 * PCIe I/O TLB entry expects that all 3 PCIe I/O windows are mapped one after
138 * another. Check for this requirement.
139 */
140static_assert(CFG_SYS_PCIE1_IO_VIRT + SZ_64K == CFG_SYS_PCIE2_IO_VIRT);
141static_assert(CFG_SYS_PCIE1_IO_PHYS + SZ_64K == CFG_SYS_PCIE2_IO_PHYS);
142static_assert(CFG_SYS_PCIE2_IO_VIRT + SZ_64K == CFG_SYS_PCIE3_IO_VIRT);
143static_assert(CFG_SYS_PCIE2_IO_PHYS + SZ_64K == CFG_SYS_PCIE3_IO_PHYS);