blob: ab33d0f3d2a247a0a967e51160d36d05fba9fd0d [file] [log] [blame]
Patrice Chotardac871ab2018-01-18 13:39:32 +01001/*
2 * Copyright (C) STMicroelectronics SA 2017
3 * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_MISC_INIT_R
12
13#define CONFIG_SYS_FLASH_BASE 0x08000000
14
15#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
16#define CONFIG_SYS_TEXT_BASE 0x08000000
17
18#define CONFIG_SYS_ICACHE_OFF
19#define CONFIG_SYS_DCACHE_OFF
20
21/*
22 * Configuration of the external SDRAM memory
23 */
24#define CONFIG_NR_DRAM_BANKS 1
25#define CONFIG_SYS_RAM_FREQ_DIV 2
26#define CONFIG_SYS_RAM_BASE 0x00000000
27#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
28#define CONFIG_SYS_LOAD_ADDR 0x00400000
29#define CONFIG_LOADADDR 0x00400000
30
31#define CONFIG_SYS_MAX_FLASH_SECT 12
32#define CONFIG_SYS_MAX_FLASH_BANKS 2
33
34#define CONFIG_ENV_OFFSET (256 << 10)
35#define CONFIG_ENV_SECT_SIZE (128 << 10)
36#define CONFIG_ENV_SIZE (8 << 10)
37
38#define CONFIG_STM32_FLASH
39
40#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
41#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
42
43#define CONFIG_CMDLINE_TAG
44#define CONFIG_SETUP_MEMORY_TAGS
45#define CONFIG_INITRD_TAG
46#define CONFIG_REVISION_TAG
47
48#define CONFIG_SYS_CBSIZE 1024
49
50#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
51
52#define CONFIG_BOOTCOMMAND \
53 "run boot_sd"
54
55#define CONFIG_EXTRA_ENV_SETTINGS \
56 "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32429i-eval.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
57
58/*
59 * Command line configuration.
60 */
61#define CONFIG_SYS_LONGHELP
62#define CONFIG_AUTO_COMPLETE
63#define CONFIG_CMDLINE_EDITING
64
65#endif /* __CONFIG_H */