blob: e7f9f6197467c6c454356d768f099d4e3cf764b0 [file] [log] [blame]
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +09001/*
2 * Configuation settings for the sh7753evb board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __SH7753EVB_H
10#define __SH7753EVB_H
11
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090012#define CONFIG_CPU_SH7753 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090013
14#define CONFIG_SYS_TEXT_BASE 0x5ff80000
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090015
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020016#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090017#undef CONFIG_SHOW_BOOT_PROGRESS
18#define CONFIG_CMDLINE_EDITING
19#define CONFIG_AUTO_COMPLETE
20
21/* MEMORY */
22#define SH7753EVB_SDRAM_BASE (0x40000000)
23#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
24
25#define CONFIG_SYS_LONGHELP
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090026#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090027#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
28
29/* SCIF */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090030#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090031
32#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
33#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
34 480 * 1024 * 1024)
35#undef CONFIG_SYS_ALT_MEMTEST
36#undef CONFIG_SYS_MEMTEST_SCRATCH
37#undef CONFIG_SYS_LOADS_BAUD_CHANGE
38
39#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
40#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
41#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
42 128 * 1024 * 1024)
43
44#define CONFIG_SYS_MONITOR_BASE 0x00000000
45#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
46#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
47#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
48
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090049/* Ether */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090050#define CONFIG_SH_ETHER_USE_PORT 0
51#define CONFIG_SH_ETHER_PHY_ADDR 18
52#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
53#define CONFIG_SH_ETHER_USE_GETHER 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090054#define CONFIG_BITBANGMII
55#define CONFIG_BITBANGMII_MULTI
56#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
57#define CONFIG_PHY_VITESSE
58
59#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
60#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
61#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
62#define SH7753EVB_ETHERNET_MAC_SIZE 17
63#define SH7753EVB_ETHERNET_NUM_CH 2
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090064
65/* SPI */
66#define CONFIG_SH_SPI 1
67#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090068
69/* MMCIF */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090070#define CONFIG_SH_MMCIF 1
71#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
72#define CONFIG_SH_MMCIF_CLK 48000000
73
74/* ENV setting */
75#define CONFIG_ENV_IS_EMBEDDED
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090076#define CONFIG_ENV_SECT_SIZE (64 * 1024)
77#define CONFIG_ENV_ADDR (0x00080000)
78#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
79#define CONFIG_ENV_OVERWRITE 1
80#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
81#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
82#define CONFIG_EXTRA_ENV_SETTINGS \
83 "netboot=bootp; bootm\0"
84
85/* Board Clock */
86#define CONFIG_SYS_CLK_FREQ 48000000
87#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
88#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
89#define CONFIG_SYS_TMU_CLK_DIV 4
90#endif /* __SH7753EVB_H */