Blame - include/configs/gose.h - filogic/uboot

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Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	1	/*
				2	* include/configs/gose.h
				3	*
				4	* Copyright (C) 2014 Renesas Electronics Corporation
				5	*
				6	* SPDX-License-Identifier: GPL-2.0
				7	*/
				8
				9	#ifndef __GOSE_H
				10	#define __GOSE_H
				11
				12	#undef DEBUG
Nobuhiro Iwamatsu	7c11273	2015-10-10 05:58:28 +0900	[diff] [blame]	13	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	14
Nobuhiro Iwamatsu	b6169ac	2014-11-10 14:34:07 +0900	[diff] [blame]	15	#include "rcar-gen2-common.h"
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	16
Nobuhiro Iwamatsu	7c11273	2015-10-10 05:58:28 +0900	[diff] [blame]	17	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	18	#define CONFIG_SYS_TEXT_BASE 0x70000000
				19	#else
				20	#define CONFIG_SYS_TEXT_BASE 0xE6304000
				21	#endif
				22
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	23	/* STACK */
Nobuhiro Iwamatsu	7c11273	2015-10-10 05:58:28 +0900	[diff] [blame]	24	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	25	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
				26	#else
				27	#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
				28	#endif
				29
				30	#define STACK_AREA_SIZE 0xC000
				31	#define LOW_LEVEL_MERAM_STACK \
				32	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
				33
				34	/* MEMORY */
Nobuhiro Iwamatsu	b6169ac	2014-11-10 14:34:07 +0900	[diff] [blame]	35	#define RCAR_GEN2_SDRAM_BASE 0x40000000
				36	#define RCAR_GEN2_SDRAM_SIZE 0x40000000
				37	#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	38
				39	/* SCIF */
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	40
				41	/* FLASH */
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	42	#define CONFIG_SPI
				43	#define CONFIG_SH_QSPI
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	44
Nobuhiro Iwamatsu	eef1f23	2014-11-06 15:42:24 +0900	[diff] [blame]	45	/* SH Ether */
Nobuhiro Iwamatsu	eef1f23	2014-11-06 15:42:24 +0900	[diff] [blame]	46	#define CONFIG_SH_ETHER_USE_PORT 0
				47	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
				48	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
				49	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
				50	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
Nobuhiro Iwamatsu	eef1f23	2014-11-06 15:42:24 +0900	[diff] [blame]	51	#define CONFIG_BITBANGMII
				52	#define CONFIG_BITBANGMII_MULTI
				53	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
				54
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	55	/* Board Clock */
				56	#define RMOBILE_XTAL_CLK 20000000u
				57	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
				58	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	59	#define CONFIG_SYS_TMU_CLK_DIV 4
				60
				61	/* I2C */
				62	#define CONFIG_SYS_I2C
				63	#define CONFIG_SYS_I2C_SH
				64	#define CONFIG_SYS_I2C_SLAVE 0x7F
				65	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	66	#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	67	#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	68	#define CONFIG_SYS_I2C_SH_SPEED2 400000
				69	#define CONFIG_SH_I2C_DATA_HIGH 4
				70	#define CONFIG_SH_I2C_DATA_LOW 5
				71	#define CONFIG_SH_I2C_CLOCK 10000000
				72
				73	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
				74
Nobuhiro Iwamatsu	87adc0a	2014-11-06 15:42:25 +0900	[diff] [blame]	75	/* USB */
Nobuhiro Iwamatsu	87adc0a	2014-11-06 15:42:25 +0900	[diff] [blame]	76	#define CONFIG_USB_EHCI_RMOBILE
				77	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
				78
Nobuhiro Iwamatsu	e02f174	2014-12-02 16:52:24 +0900	[diff] [blame]	79	/* Module stop status bits */
				80	/* INTC-RT */
				81	#define CONFIG_SMSTP0_ENA 0x00400000
				82	/* MSIF */
				83	#define CONFIG_SMSTP2_ENA 0x00002000
				84	/* INTC-SYS, IRQC */
				85	#define CONFIG_SMSTP4_ENA 0x00000180
				86	/* SCIF0 */
				87	#define CONFIG_SMSTP7_ENA 0x00200000
				88
Nobuhiro Iwamatsu	161af50	2014-11-12 11:29:39 +0900	[diff] [blame]	89	/* SDHI */
Nobuhiro Iwamatsu	161af50	2014-11-12 11:29:39 +0900	[diff] [blame]	90	#define CONFIG_SH_SDHI_FREQ 97500000
				91
Nobuhiro Iwamatsu	7e40563	2014-11-06 15:39:28 +0900	[diff] [blame]	92	#endif /* __GOSE_H */