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Andy Fleming60ca78b2011-04-07 21:56:05 -05001/*
2 * Micrel PHY drivers
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming60ca78b2011-04-07 21:56:05 -05005 *
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * author Andy Fleming
David Andreyf0d83c42013-02-06 22:18:37 +01008 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
Alexandru Gagniuc757bb672017-07-07 11:36:57 -07009 * (C) Copyright 2017 Adaptrum, Inc.
10 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
Andy Fleming60ca78b2011-04-07 21:56:05 -050011 */
Philipp Tomsich2e1ba7d2017-09-11 22:04:14 +020012
Troy Kisky80b6b092012-02-07 14:08:48 +000013#include <config.h>
14#include <common.h>
Marek Vasut1005ce52015-12-05 17:41:58 +010015#include <dm.h>
16#include <errno.h>
Troy Kisky80b6b092012-02-07 14:08:48 +000017#include <micrel.h>
Andy Fleming60ca78b2011-04-07 21:56:05 -050018#include <phy.h>
19
Marek Vasut1005ce52015-12-05 17:41:58 +010020DECLARE_GLOBAL_DATA_PTR;
21
Pavel Machek5f022112014-09-09 14:26:51 +020022/*
David Andreyf0d83c42013-02-06 22:18:37 +010023 * KSZ9021 - KSZ9031 common
24 */
25
26#define MII_KSZ90xx_PHY_CTL 0x1f
27#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
28#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
29#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
30#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
31
Alexandru Gagniuc757bb672017-07-07 11:36:57 -070032/* KSZ9021 PHY Registers */
33#define MII_KSZ9021_EXTENDED_CTRL 0x0b
34#define MII_KSZ9021_EXTENDED_DATAW 0x0c
35#define MII_KSZ9021_EXTENDED_DATAR 0x0d
36
37#define CTRL1000_PREFER_MASTER (1 << 10)
38#define CTRL1000_CONFIG_MASTER (1 << 11)
39#define CTRL1000_MANUAL_CONFIG (1 << 12)
40
41/* KSZ9031 PHY Registers */
42#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
43#define MII_KSZ9031_MMD_REG_DATA 0x0e
44
David Andreyf0d83c42013-02-06 22:18:37 +010045static int ksz90xx_startup(struct phy_device *phydev)
46{
47 unsigned phy_ctl;
Michal Simek5ff89662016-05-18 12:46:12 +020048 int ret;
49
50 ret = genphy_update_link(phydev);
51 if (ret)
52 return ret;
53
David Andreyf0d83c42013-02-06 22:18:37 +010054 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
55
56 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
57 phydev->duplex = DUPLEX_FULL;
58 else
59 phydev->duplex = DUPLEX_HALF;
60
61 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
62 phydev->speed = SPEED_1000;
63 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
64 phydev->speed = SPEED_100;
65 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
66 phydev->speed = SPEED_10;
67 return 0;
68}
David Andreyf0d83c42013-02-06 22:18:37 +010069
Marek Vasut1005ce52015-12-05 17:41:58 +010070/* Common OF config bits for KSZ9021 and KSZ9031 */
Marek Vasut1005ce52015-12-05 17:41:58 +010071#ifdef CONFIG_DM_ETH
72struct ksz90x1_reg_field {
73 const char *name;
74 const u8 size; /* Size of the bitfield, in bits */
75 const u8 off; /* Offset from bit 0 */
76 const u8 dflt; /* Default value */
77};
78
79struct ksz90x1_ofcfg {
80 const u16 reg;
81 const u16 devad;
82 const struct ksz90x1_reg_field *grp;
83 const u16 grpsz;
84};
85
86static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
87 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
88 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
89};
90
91static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
92 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
93 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
94};
95
Alexandru Gagniuc757bb672017-07-07 11:36:57 -070096static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
97 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
98 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
99};
100
101static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
102 { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
103};
104
105static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
106 { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
107};
108
Marek Vasut1005ce52015-12-05 17:41:58 +0100109static int ksz90x1_of_config_group(struct phy_device *phydev,
110 struct ksz90x1_ofcfg *ofcfg)
111{
112 struct udevice *dev = phydev->dev;
113 struct phy_driver *drv = phydev->drv;
Dinh Nguyen826df7a2016-01-27 15:46:00 -0600114 const int ps_to_regval = 60;
Marek Vasut1005ce52015-12-05 17:41:58 +0100115 int val[4];
116 int i, changed = 0, offset, max;
117 u16 regval = 0;
118
119 if (!drv || !drv->writeext)
120 return -EOPNOTSUPP;
121
122 for (i = 0; i < ofcfg->grpsz; i++) {
Philipp Tomsich2e1ba7d2017-09-11 22:04:14 +0200123 val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
Marek Vasut1005ce52015-12-05 17:41:58 +0100124 offset = ofcfg->grp[i].off;
125 if (val[i] == -1) {
126 /* Default register value for KSZ9021 */
127 regval |= ofcfg->grp[i].dflt << offset;
128 } else {
129 changed = 1; /* Value was changed in OF */
130 /* Calculate the register value and fix corner cases */
131 if (val[i] > ps_to_regval * 0xf) {
132 max = (1 << ofcfg->grp[i].size) - 1;
133 regval |= max << offset;
134 } else {
135 regval |= (val[i] / ps_to_regval) << offset;
136 }
137 }
138 }
139
140 if (!changed)
141 return 0;
142
143 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
144}
Marek Vasut1005ce52015-12-05 17:41:58 +0100145
146static int ksz9021_of_config(struct phy_device *phydev)
147{
148 struct ksz90x1_ofcfg ofcfg[] = {
149 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
150 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
151 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
152 };
153 int i, ret = 0;
154
Marek Vasut0c766302016-11-14 15:08:42 +0100155 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
Marek Vasut1005ce52015-12-05 17:41:58 +0100156 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
157 if (ret)
158 return ret;
Marek Vasut0c766302016-11-14 15:08:42 +0100159 }
Marek Vasut1005ce52015-12-05 17:41:58 +0100160
161 return 0;
162}
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700163
164static int ksz9031_of_config(struct phy_device *phydev)
165{
166 struct ksz90x1_ofcfg ofcfg[] = {
167 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
168 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
169 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
170 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
171 };
172 int i, ret = 0;
173
174 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
175 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
176 if (ret)
177 return ret;
178 }
179
180 return 0;
181}
182
183static int ksz9031_center_flp_timing(struct phy_device *phydev)
184{
185 struct phy_driver *drv = phydev->drv;
186 int ret = 0;
187
188 if (!drv || !drv->writeext)
189 return -EOPNOTSUPP;
190
191 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
192 if (ret)
193 return ret;
194
195 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
196 return ret;
197}
198
199#else /* !CONFIG_DM_ETH */
Marek Vasut1005ce52015-12-05 17:41:58 +0100200static int ksz9021_of_config(struct phy_device *phydev)
201{
202 return 0;
203}
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700204
205static int ksz9031_of_config(struct phy_device *phydev)
206{
207 return 0;
208}
209
210static int ksz9031_center_flp_timing(struct phy_device *phydev)
211{
212 return 0;
213}
Marek Vasut1005ce52015-12-05 17:41:58 +0100214#endif
215
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700216/*
217 * KSZ9021
218 */
Troy Kisky80b6b092012-02-07 14:08:48 +0000219int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
220{
221 /* extended registers */
222 phy_write(phydev, MDIO_DEVAD_NONE,
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700223 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
Troy Kisky80b6b092012-02-07 14:08:48 +0000224 return phy_write(phydev, MDIO_DEVAD_NONE,
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700225 MII_KSZ9021_EXTENDED_DATAW, val);
Troy Kisky80b6b092012-02-07 14:08:48 +0000226}
227
228int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
229{
230 /* extended registers */
231 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
232 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
233}
234
Stefano Babica8aa2992013-09-02 15:42:31 +0200235
236static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700237 int regnum)
Stefano Babica8aa2992013-09-02 15:42:31 +0200238{
239 return ksz9021_phy_extended_read(phydev, regnum);
240}
241
242static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700243 int devaddr, int regnum, u16 val)
Stefano Babica8aa2992013-09-02 15:42:31 +0200244{
245 return ksz9021_phy_extended_write(phydev, regnum, val);
246}
247
Troy Kisky80b6b092012-02-07 14:08:48 +0000248static int ksz9021_config(struct phy_device *phydev)
249{
250 unsigned ctrl1000 = 0;
251 const unsigned master = CTRL1000_PREFER_MASTER |
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700252 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
Troy Kisky80b6b092012-02-07 14:08:48 +0000253 unsigned features = phydev->drv->features;
Marek Vasut1005ce52015-12-05 17:41:58 +0100254 int ret;
255
256 ret = ksz9021_of_config(phydev);
257 if (ret)
258 return ret;
Troy Kisky80b6b092012-02-07 14:08:48 +0000259
Simon Glass64b723f2017-08-03 12:22:12 -0600260 if (env_get("disable_giga"))
Troy Kisky80b6b092012-02-07 14:08:48 +0000261 features &= ~(SUPPORTED_1000baseT_Half |
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700262 SUPPORTED_1000baseT_Full);
Troy Kisky80b6b092012-02-07 14:08:48 +0000263 /* force master mode for 1000BaseT due to chip errata */
264 if (features & SUPPORTED_1000baseT_Half)
265 ctrl1000 |= ADVERTISE_1000HALF | master;
266 if (features & SUPPORTED_1000baseT_Full)
267 ctrl1000 |= ADVERTISE_1000FULL | master;
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700268 phydev->advertising = features;
269 phydev->supported = features;
Troy Kisky80b6b092012-02-07 14:08:48 +0000270 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
271 genphy_config_aneg(phydev);
272 genphy_restart_aneg(phydev);
273 return 0;
274}
275
Troy Kisky80b6b092012-02-07 14:08:48 +0000276static struct phy_driver ksz9021_driver = {
277 .name = "Micrel ksz9021",
278 .uid = 0x221610,
279 .mask = 0xfffff0,
280 .features = PHY_GBIT_FEATURES,
281 .config = &ksz9021_config,
David Andreyf0d83c42013-02-06 22:18:37 +0100282 .startup = &ksz90xx_startup,
Troy Kisky80b6b092012-02-07 14:08:48 +0000283 .shutdown = &genphy_shutdown,
Stefano Babica8aa2992013-09-02 15:42:31 +0200284 .writeext = &ksz9021_phy_extwrite,
285 .readext = &ksz9021_phy_extread,
Troy Kisky80b6b092012-02-07 14:08:48 +0000286};
287
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700288/*
David Andreyf0d83c42013-02-06 22:18:37 +0100289 * KSZ9031
290 */
SARTRE Leoeaf68ac2013-04-30 16:57:25 +0200291int ksz9031_phy_extended_write(struct phy_device *phydev,
292 int devaddr, int regnum, u16 mode, u16 val)
293{
294 /*select register addr for mmd*/
295 phy_write(phydev, MDIO_DEVAD_NONE,
296 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
297 /*select register for mmd*/
298 phy_write(phydev, MDIO_DEVAD_NONE,
299 MII_KSZ9031_MMD_REG_DATA, regnum);
300 /*setup mode*/
301 phy_write(phydev, MDIO_DEVAD_NONE,
302 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
303 /*write the value*/
304 return phy_write(phydev, MDIO_DEVAD_NONE,
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700305 MII_KSZ9031_MMD_REG_DATA, val);
SARTRE Leoeaf68ac2013-04-30 16:57:25 +0200306}
307
308int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
309 int regnum, u16 mode)
310{
311 phy_write(phydev, MDIO_DEVAD_NONE,
312 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
313 phy_write(phydev, MDIO_DEVAD_NONE,
314 MII_KSZ9031_MMD_REG_DATA, regnum);
315 phy_write(phydev, MDIO_DEVAD_NONE,
316 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
317 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
318}
319
Stefano Babica8aa2992013-09-02 15:42:31 +0200320static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
321 int regnum)
322{
323 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
324 MII_KSZ9031_MOD_DATA_NO_POST_INC);
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700325}
Stefano Babica8aa2992013-09-02 15:42:31 +0200326
327static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
328 int devaddr, int regnum, u16 val)
329{
330 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700331 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
332}
Stefano Babica8aa2992013-09-02 15:42:31 +0200333
Marek Vasut1005ce52015-12-05 17:41:58 +0100334static int ksz9031_config(struct phy_device *phydev)
335{
336 int ret;
Sebastien Bourdelin3a6e0332017-07-28 15:59:22 -0400337
Marek Vasut1005ce52015-12-05 17:41:58 +0100338 ret = ksz9031_of_config(phydev);
339 if (ret)
340 return ret;
Ash Charles3f55bb62016-10-21 17:31:33 -0400341 ret = ksz9031_center_flp_timing(phydev);
342 if (ret)
343 return ret;
Sebastien Bourdelin3a6e0332017-07-28 15:59:22 -0400344
345 /* add an option to disable the gigabit feature of this PHY */
Simon Glass64b723f2017-08-03 12:22:12 -0600346 if (env_get("disable_giga")) {
Sebastien Bourdelin3a6e0332017-07-28 15:59:22 -0400347 unsigned features;
348 unsigned bmcr;
349
350 /* disable speed 1000 in features supported by the PHY */
351 features = phydev->drv->features;
352 features &= ~(SUPPORTED_1000baseT_Half |
353 SUPPORTED_1000baseT_Full);
354 phydev->advertising = phydev->supported = features;
355
356 /* disable speed 1000 in Basic Control Register */
357 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
358 bmcr &= ~(1 << 6);
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
360
361 /* disable speed 1000 in 1000Base-T Control Register */
362 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
363
364 /* start autoneg */
365 genphy_config_aneg(phydev);
366 genphy_restart_aneg(phydev);
367
368 return 0;
369 }
370
Marek Vasut1005ce52015-12-05 17:41:58 +0100371 return genphy_config(phydev);
372}
Stefano Babica8aa2992013-09-02 15:42:31 +0200373
David Andreyf0d83c42013-02-06 22:18:37 +0100374static struct phy_driver ksz9031_driver = {
375 .name = "Micrel ksz9031",
376 .uid = 0x221620,
Stefano Babicd9e36ad2013-09-02 15:42:29 +0200377 .mask = 0xfffff0,
David Andreyf0d83c42013-02-06 22:18:37 +0100378 .features = PHY_GBIT_FEATURES,
Marek Vasut1005ce52015-12-05 17:41:58 +0100379 .config = &ksz9031_config,
David Andreyf0d83c42013-02-06 22:18:37 +0100380 .startup = &ksz90xx_startup,
381 .shutdown = &genphy_shutdown,
Stefano Babica8aa2992013-09-02 15:42:31 +0200382 .writeext = &ksz9031_phy_extwrite,
383 .readext = &ksz9031_phy_extread,
David Andreyf0d83c42013-02-06 22:18:37 +0100384};
385
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700386int phy_micrel_ksz90x1_init(void)
Andy Fleming60ca78b2011-04-07 21:56:05 -0500387{
Troy Kisky80b6b092012-02-07 14:08:48 +0000388 phy_register(&ksz9021_driver);
David Andreyf0d83c42013-02-06 22:18:37 +0100389 phy_register(&ksz9031_driver);
Andy Fleming60ca78b2011-04-07 21:56:05 -0500390 return 0;
391}