Jagan Teki | 0d6d48b | 2016-10-08 18:00:11 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Amarula Solutions B.V. |
| 3 | * Copyright (C) 2016 Engicam S.r.l. |
| 4 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Jagan Teki | 0d6d48b | 2016-10-08 18:00:11 +0530 | [diff] [blame] | 10 | |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/gpio.h> |
| 13 | #include <linux/sizes.h> |
| 14 | |
| 15 | #include <asm/arch/clock.h> |
Jagan Teki | 12c8e2d | 2016-10-08 18:00:13 +0530 | [diff] [blame] | 16 | #include <asm/arch/crm_regs.h> |
Jagan Teki | 0d6d48b | 2016-10-08 18:00:11 +0530 | [diff] [blame] | 17 | #include <asm/arch/iomux.h> |
| 18 | #include <asm/arch/mx6-pins.h> |
| 19 | #include <asm/arch/sys_proto.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 20 | #include <asm/mach-imx/iomux-v3.h> |
| 21 | #include <asm/mach-imx/video.h> |
Jagan Teki | 0d6d48b | 2016-10-08 18:00:11 +0530 | [diff] [blame] | 22 | |
Jagan Teki | c5d8681 | 2017-05-07 02:43:14 +0530 | [diff] [blame] | 23 | #include "../common/board.h" |
| 24 | |
Jagan Teki | 0d6d48b | 2016-10-08 18:00:11 +0530 | [diff] [blame] | 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
Jagan Teki | 0313c13 | 2016-10-25 11:53:23 +0530 | [diff] [blame] | 27 | #ifdef CONFIG_NAND_MXS |
Jagan Teki | 0313c13 | 2016-10-25 11:53:23 +0530 | [diff] [blame] | 28 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) |
| 29 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ |
| 30 | PAD_CTL_SRE_FAST) |
| 31 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) |
| 32 | |
Jagan Teki | 515bd00 | 2017-11-21 00:02:16 +0530 | [diff] [blame] | 33 | static iomux_v3_cfg_t gpmi_pads[] = { |
Jagan Teki | 0313c13 | 2016-10-25 11:53:23 +0530 | [diff] [blame] | 34 | IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 35 | IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 36 | IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 37 | IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), |
| 38 | IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 39 | IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 40 | IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 41 | IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 42 | IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 43 | IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 44 | IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 45 | IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 46 | IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 47 | IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 48 | IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
| 49 | }; |
| 50 | |
Jagan Teki | c5d8681 | 2017-05-07 02:43:14 +0530 | [diff] [blame] | 51 | void setup_gpmi_nand(void) |
Jagan Teki | 0313c13 | 2016-10-25 11:53:23 +0530 | [diff] [blame] | 52 | { |
| 53 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 54 | |
| 55 | /* config gpmi nand iomux */ |
| 56 | SETUP_IOMUX_PADS(gpmi_pads); |
| 57 | |
| 58 | /* gate ENFC_CLK_ROOT clock first,before clk source switch */ |
| 59 | clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); |
| 60 | |
| 61 | /* config gpmi and bch clock to 100 MHz */ |
| 62 | clrsetbits_le32(&mxc_ccm->cs2cdr, |
| 63 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | |
| 64 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | |
| 65 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, |
| 66 | MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | |
| 67 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | |
| 68 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); |
| 69 | |
| 70 | /* enable ENFC_CLK_ROOT clock */ |
| 71 | setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); |
| 72 | |
| 73 | /* enable gpmi and bch clock gating */ |
| 74 | setbits_le32(&mxc_ccm->CCGR4, |
| 75 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
| 76 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
| 77 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
| 78 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
| 79 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); |
| 80 | |
| 81 | /* enable apbh clock gating */ |
| 82 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
| 83 | } |
| 84 | #endif |
| 85 | |
Jagan Teki | b62dc48 | 2016-12-06 00:00:55 +0100 | [diff] [blame] | 86 | #if defined(CONFIG_VIDEO_IPUV3) |
| 87 | static iomux_v3_cfg_t const rgb_pads[] = { |
| 88 | IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), |
| 89 | IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), |
| 90 | IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), |
| 91 | IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), |
| 92 | IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), |
| 93 | IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), |
| 94 | IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), |
| 95 | IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), |
| 96 | IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), |
| 97 | IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), |
| 98 | IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), |
| 99 | IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), |
| 100 | IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), |
| 101 | IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), |
| 102 | IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), |
| 103 | IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), |
| 104 | IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), |
| 105 | IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), |
| 106 | IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), |
| 107 | IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), |
| 108 | IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), |
| 109 | IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), |
| 110 | }; |
| 111 | |
| 112 | static void enable_rgb(struct display_info_t const *dev) |
| 113 | { |
| 114 | SETUP_IOMUX_PADS(rgb_pads); |
| 115 | } |
| 116 | |
| 117 | struct display_info_t const displays[] = { |
| 118 | { |
| 119 | .bus = -1, |
| 120 | .addr = 0, |
| 121 | .pixfmt = IPU_PIX_FMT_RGB666, |
| 122 | .detect = NULL, |
| 123 | .enable = enable_rgb, |
| 124 | .mode = { |
| 125 | .name = "Amp-WD", |
| 126 | .refresh = 60, |
| 127 | .xres = 800, |
| 128 | .yres = 480, |
| 129 | .pixclock = 30000, |
| 130 | .left_margin = 30, |
| 131 | .right_margin = 30, |
| 132 | .upper_margin = 5, |
| 133 | .lower_margin = 5, |
| 134 | .hsync_len = 64, |
| 135 | .vsync_len = 20, |
| 136 | .sync = FB_SYNC_EXT, |
| 137 | .vmode = FB_VMODE_NONINTERLACED |
| 138 | } |
| 139 | }, |
| 140 | }; |
| 141 | |
| 142 | size_t display_count = ARRAY_SIZE(displays); |
| 143 | |
Jagan Teki | c5d8681 | 2017-05-07 02:43:14 +0530 | [diff] [blame] | 144 | void setup_display(void) |
Jagan Teki | b62dc48 | 2016-12-06 00:00:55 +0100 | [diff] [blame] | 145 | { |
| 146 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 147 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 148 | int reg; |
| 149 | |
| 150 | enable_ipu_clock(); |
| 151 | |
| 152 | /* Turn on LDB0,IPU,IPU DI0 clocks */ |
| 153 | reg = __raw_readl(&mxc_ccm->CCGR3); |
| 154 | reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); |
| 155 | writel(reg, &mxc_ccm->CCGR3); |
| 156 | |
| 157 | /* set LDB0, LDB1 clk select to 011/011 */ |
| 158 | reg = readl(&mxc_ccm->cs2cdr); |
| 159 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | |
| 160 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
| 161 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | |
| 162 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
| 163 | writel(reg, &mxc_ccm->cs2cdr); |
| 164 | |
| 165 | reg = readl(&mxc_ccm->cscmr2); |
| 166 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; |
| 167 | writel(reg, &mxc_ccm->cscmr2); |
| 168 | |
| 169 | reg = readl(&mxc_ccm->chsccdr); |
| 170 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << |
| 171 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
| 172 | writel(reg, &mxc_ccm->chsccdr); |
| 173 | |
| 174 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | |
| 175 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | |
| 176 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | |
| 177 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | |
| 178 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | |
| 179 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | |
| 180 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
| 181 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | |
| 182 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; |
| 183 | writel(reg, &iomux->gpr[2]); |
| 184 | |
| 185 | reg = readl(&iomux->gpr[3]); |
| 186 | reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | |
| 187 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << |
| 188 | IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); |
| 189 | writel(reg, &iomux->gpr[3]); |
| 190 | } |
| 191 | #endif /* CONFIG_VIDEO_IPUV3 */ |
Jagan Teki | 515bd00 | 2017-11-21 00:02:16 +0530 | [diff] [blame] | 192 | |
| 193 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 194 | int board_mmc_get_env_dev(int devno) |
| 195 | { |
Jagan Teki | dc91b40 | 2017-11-21 00:02:17 +0530 | [diff] [blame] | 196 | /* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */ |
| 197 | return (devno == 0) ? 0: (devno - 1); |
Jagan Teki | 515bd00 | 2017-11-21 00:02:16 +0530 | [diff] [blame] | 198 | } |
| 199 | #endif |