Christophe Leroy | 0ae15b9 | 2017-07-13 15:10:00 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2017 |
| 3 | * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/processor.h> |
| 10 | #include <asm/ppc.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/mmu.h> |
| 13 | |
| 14 | int icache_status(void) |
| 15 | { |
| 16 | return !!(mfspr(IC_CST) & IDC_ENABLED); |
| 17 | } |
| 18 | |
| 19 | void icache_enable(void) |
| 20 | { |
| 21 | sync(); |
| 22 | mtspr(IC_CST, IDC_INVALL); |
| 23 | mtspr(IC_CST, IDC_ENABLE); |
| 24 | } |
| 25 | |
| 26 | void icache_disable(void) |
| 27 | { |
| 28 | sync(); |
| 29 | mtspr(IC_CST, IDC_DISABLE); |
| 30 | } |
| 31 | |
| 32 | int dcache_status(void) |
| 33 | { |
| 34 | return !!(mfspr(IC_CST) & IDC_ENABLED); |
| 35 | } |
| 36 | |
| 37 | void dcache_enable(void) |
| 38 | { |
| 39 | mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */ |
| 40 | mtspr(DC_CST, IDC_INVALL); |
| 41 | mtspr(DC_CST, IDC_ENABLE); |
| 42 | } |
| 43 | |
| 44 | void dcache_disable(void) |
| 45 | { |
| 46 | sync(); |
| 47 | mtspr(DC_CST, IDC_DISABLE); |
| 48 | mtspr(DC_CST, IDC_INVALL); |
| 49 | } |