blob: d7026aa867da29e034b6b73d6c861fb69719ed7b [file] [log] [blame]
Jorge Ramirez-Ortiz92c1eff2018-01-10 11:33:49 +01001/*
2 * Qualcomm APQ8016, APQ8096
3 *
4 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8#ifndef _CLOCK_SNAPDRAGON_H
9#define _CLOCK_SNAPDRAGON_H
10
11#define CFG_CLK_SRC_CXO (0 << 8)
12#define CFG_CLK_SRC_GPLL0 (1 << 8)
13#define CFG_CLK_SRC_MASK (7 << 8)
14
15struct gpll0_ctrl {
16 uintptr_t status;
17 int status_bit;
18 uintptr_t ena_vote;
19 int vote_bit;
20};
21
22struct bcr_regs {
23 uintptr_t cfg_rcgr;
24 uintptr_t cmd_rcgr;
25 uintptr_t M;
26 uintptr_t N;
27 uintptr_t D;
28};
29
30struct msm_clk_priv {
31 phys_addr_t base;
32};
33
34void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
35void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
36void clk_enable_cbc(phys_addr_t cbcr);
37void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
38 int div, int m, int n, int source);
39
40#endif