| Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2013-2015 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch-tegra/tegra_i2c.h> |
| 11 | #include "max77620_init.h" |
| 12 | |
| 13 | /* MAX77620-PMIC-specific early init code - get CPU rails up, etc */ |
| 14 | |
| 15 | void tegra_i2c_ll_write_addr(uint addr, uint config) |
| 16 | { |
| 17 | struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; |
| 18 | |
| 19 | writel(addr, ®->cmd_addr0); |
| 20 | writel(config, ®->cnfg); |
| 21 | } |
| 22 | |
| 23 | void tegra_i2c_ll_write_data(uint data, uint config) |
| 24 | { |
| 25 | struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; |
| 26 | |
| 27 | writel(data, ®->cmd_data1); |
| 28 | writel(config, ®->cnfg); |
| 29 | } |
| 30 | |
| 31 | void pmic_enable_cpu_vdd(void) |
| 32 | { |
| 33 | uint reg; |
| 34 | debug("%s entry\n", __func__); |
| 35 | |
| 36 | /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ |
| 37 | debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__); |
| 38 | /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */ |
| 39 | reg = 0x0900 | MAX77620_GPIO5_REG; |
| 40 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 41 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 42 | udelay(10 * 1000); |
| 43 | |
| 44 | /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */ |
| 45 | debug("%s: Setting GPIO1 to enable HDMI\n", __func__); |
| 46 | reg = 0x0900 | MAX77620_GPIO1_REG; |
| 47 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 48 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 49 | udelay(10 * 1000); |
| 50 | |
| 51 | /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ |
| 52 | reg = 0x1C00 | MAX77620_AME_GPIO; |
| 53 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 54 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 55 | udelay(10 * 1000); |
| 56 | |
| 57 | /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */ |
| 58 | debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n", |
| 59 | __func__); |
| 60 | /* bit1=0, SD1 remote sense disabled */ |
| 61 | reg = 0x0400 | MAX77620_CNFG2SD_REG; |
| 62 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 63 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 64 | udelay(10 * 1000); |
| 65 | |
| 66 | /* SD1 output = 1.125V */ |
| 67 | reg = 0x2A00 | MAX77620_SD1_REG; |
| 68 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 69 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 70 | udelay(10 * 1000); |
| 71 | |
| 72 | debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); |
| 73 | /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ |
| 74 | reg = 0xF200 | MAX77620_CNFG1_L2_REG; |
| 75 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 76 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 77 | udelay(10 * 1000); |
| 78 | |
| 79 | debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__); |
| 80 | /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ |
| 81 | reg = 0xCA00 | MAX77620_CNFG1_L1_REG; |
| 82 | tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); |
| 83 | tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); |
| 84 | udelay(10 * 1000); |
| 85 | } |