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git01.mediatek.com / filogic / uboot / 2207335a98969fe7dda5952870dd50a31198ec0f / . / drivers / pinctrl / mediatek / pinctrl-mt7981.c
blob: d8875241cb61c3192e8c7ee2a3df263d032d9deb [file] [log] [blame]
developer22073352022-09-09 19:59:55 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * The MT7981 driver based on Linux generic pinctrl binding.
4 *
5 * Copyright (C) 2022 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9#include <dm.h>
10#include "pinctrl-mtk-common.h"
11
12#define MT7981_TYPE0_PIN(_number, _name) \
13 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
14
15#define MT7981_TYPE1_PIN(_number, _name) \
16 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
17
18#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
19 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \
20 _s_bit, _x_bits, 32, 0)
21
22#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
23 _x_bits) \
24 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
25 _x_bits, 32, 0)
26
27/**
28 * enum - Locking variants of the iocfg bases
29 *
30 * MT7981 have multiple bases to program pin configuration listed as the below:
31 * iocfg_rt:0x11c00000, iocfg_rm:0x11c10000, iocfg_rb:0x11d20000,
32 * iocfg_lb:0x11e00000, iocfg_bl:0x11e20000, iocfg_tm:0x11f00000,
33 * iocfg_tl:0x11f10000,
34 * _i_based could be used to indicate what base the pin should be mapped into.
35 *
36 * Each iocfg register base control different group of pads on the SoC
37 *
38 *
39 * chip carrier
40 *
41 * A B C D E F G H
42 * +------------------------+
43 * 8 | o o o o o o o o |
44 * 7 | o o o o o o o o |
45 * 6 | o o o o o o o o |
46 * 5 | o o o o o o o o |
47 * 4 | o o o o o o o o |
48 * 3 | o o o o o o o o |
49 * 2 | o o o o o o o o |
50 * 1 | o o o o o o o o |
51 * +------------------------+
52 *
53 * inside Chip carrier
54 *
55 * A B C D E F G H
56 * +------------------------+
57 * 8 | |
58 * 7 | TL TM |
59 * 6 | +---------+ |
60 * 5 | | | RT |
61 * 4 | | | RM |
62 * 3 | LB | | RB |
63 * 2 | +---------+ |
64 * 1 | BL |
65 * +------------------------+
66 *
67 */
68
69enum {
70 GPIO_BASE,
71 IOCFG_RT_BASE,
72 IOCFG_RM_BASE,
73 IOCFG_RB_BASE,
74 IOCFG_LB_BASE,
75 IOCFG_BL_BASE,
76 IOCFG_TM_BASE,
77 IOCFG_TL_BASE,
78};
79
80static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
81 PIN_FIELD_GPIO(0, 56, 0x300, 0x10, 0, 4),
82};
83
84static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
85 PIN_FIELD_GPIO(0, 56, 0x0, 0x10, 0, 1),
86};
87
88static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
89 PIN_FIELD_GPIO(0, 56, 0x200, 0x10, 0, 1),
90};
91
92static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
93 PIN_FIELD_GPIO(0, 56, 0x100, 0x10, 0, 1),
94};
95
96static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
97 PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
98 PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
99 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
100 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
101 PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
102 PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
103 PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
104 PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
105 PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
106 PIN_FIELD_BASE(9, 9, 4, 0x20, 0x10, 9, 1),
107
108 PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
109 PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
110 PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
111 PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
112
113 PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
114
115 PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
116 PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
117 PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
118 PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
119 PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
120 PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
121 PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
122 PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
123 PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
124 PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
125 PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
126
127 PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
128 PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
129 PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
130 PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
131 PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
132 PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
133
134 PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
135 PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
136
137 PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
138 PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
139
140 PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
141 PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
142 PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
143 PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
144
145 PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
146 PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
147 PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
148 PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
149 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
150 PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
151 PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
152 PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
153 PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
154 PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
155
156 PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
157 PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
158 PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
159 PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
160 PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
161 PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
162 PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
163};
164
165static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
166 PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
167 PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
168 PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
169 PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
170 PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
171 PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
172 PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
173 PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
174 PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
175 PIN_FIELD_BASE(9, 9, 4, 0x80, 0x10, 9, 1),
176
177 PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
178 PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
179 PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
180 PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
181
182 PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
183
184 PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
185 PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
186 PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
187 PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
188 PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
189 PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
190 PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
191 PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
192 PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
193 PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
194 PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
195
196 PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
197 PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
198 PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
199 PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
200 PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
201 PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
202
203 PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
204 PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
205
206 PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
207 PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
208
209 PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
210 PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
211 PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
212 PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
213
214 PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
215 PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
216 PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
217 PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
218 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
219 PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
220 PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
221 PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
222 PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
223 PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
224
225 PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
226 PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
227 PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
228 PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
229 PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
230 PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
231 PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
232};
233
234static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
235 PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
236 PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
237 PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
238 PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
239 PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
240 PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
241 PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
242 PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
243 PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
244 PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
245
246 PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
247 PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
248 PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
249 PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
250 PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
251 PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
252 PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
253};
254
255static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
256 PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
257 PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
258 PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
259 PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
260 PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
261 PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
262 PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
263 PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
264 PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
265 PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
266
267 PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
268 PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
269 PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
270 PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
271 PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
272 PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
273 PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
274};
275
276static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
277 PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
278 PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
279
280 PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
281
282 PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
283 PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
284 PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
285 PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
286 PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
287 PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
288 PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 27, 3),
289
290 PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
291 PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
292 PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
293 PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
294
295 PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
296
297 PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
298 PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
299 PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
300 PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
301 PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
302 PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
303 PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
304 PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
305 PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
306 PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
307 PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
308
309 PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
310 PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
311 PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
312 PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
313 PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
314 PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
315
316 PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
317 PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
318
319 PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
320 PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
321
322 PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
323 PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
324 PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
325 PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
326
327 PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
328 PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
329 PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
330 PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
331 PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
332 PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
333 PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
334 PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
335 PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
336 PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
337
338 PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
339 PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
340 PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
341 PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
342 PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
343 PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
344 PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
345};
346
347static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
348 PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
349 PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
350 PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
351 PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
352 PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
353 PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
354 PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
355 PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
356 PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
357 PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 9, 1),
358
359 PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
360 PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
361 PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
362 PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
363
364 PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
365
366 PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
367 PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
368 PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
369 PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
370 PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
371 PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
372 PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
373 PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
374 PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
375 PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
376 PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
377
378 PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
379 PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
380 PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
381 PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
382 PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
383 PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
384
385 PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
386 PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
387
388 PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
389 PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
390
391 PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
392 PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
393 PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
394 PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
395};
396
397static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
398 PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
399 PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
400 PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
401 PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
402 PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
403 PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
404 PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
405 PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
406 PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
407 PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 9, 1),
408
409 PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
410 PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
411 PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
412 PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
413
414 PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
415
416 PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
417 PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
418 PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
419 PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
420 PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
421 PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
422 PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
423 PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
424 PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
425 PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
426 PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
427
428 PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
429 PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
430 PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
431 PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
432 PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
433 PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
434
435 PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
436 PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
437
438 PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
439 PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
440
441 PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
442 PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
443 PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
444 PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
445};
446
447static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
448 PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
449 PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
450 PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
451 PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
452 PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
453 PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
454 PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
455 PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
456 PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
457 PIN_FIELD_BASE(9, 9, 4, 0x50, 0x10, 9, 1),
458
459 PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
460 PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
461 PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
462 PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
463
464 PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
465
466 PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
467 PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
468 PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
469 PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
470 PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
471 PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
472 PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
473 PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
474 PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
475 PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
476 PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
477
478 PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
479 PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
480 PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
481 PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
482 PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
483 PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
484
485 PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
486 PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
487
488 PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
489 PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
490
491 PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
492 PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
493 PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
494 PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
495};
496
497static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
498 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
499 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
500 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
501 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
502 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
503 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
504 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
505 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
506 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
507 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
508 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
509 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
510};
511
512static const struct mtk_pin_desc mt7981_pins[] = {
513 MT7981_TYPE0_PIN(0, "GPIO_WPS"),
514 MT7981_TYPE0_PIN(1, "GPIO_RESET"),
515 MT7981_TYPE0_PIN(2, "SYS_WATCHDOG"),
516 MT7981_TYPE0_PIN(3, "PCIE_PERESET_N"),
517 MT7981_TYPE0_PIN(4, "JTAG_JTDO"),
518 MT7981_TYPE0_PIN(5, "JTAG_JTDI"),
519 MT7981_TYPE0_PIN(6, "JTAG_JTMS"),
520 MT7981_TYPE0_PIN(7, "JTAG_JTCLK"),
521 MT7981_TYPE0_PIN(8, "JTAG_JTRST_N"),
522 MT7981_TYPE0_PIN(9, "WO_JTAG_JTDO"),
523 MT7981_TYPE0_PIN(10, "WO_JTAG_JTDI"),
524 MT7981_TYPE0_PIN(11, "WO_JTAG_JTMS"),
525 MT7981_TYPE0_PIN(12, "WO_JTAG_JTCLK"),
526 MT7981_TYPE0_PIN(13, "WO_JTAG_JTRST_N"),
527 MT7981_TYPE0_PIN(14, "USB_VBUS"),
528 MT7981_TYPE0_PIN(15, "PWM0"),
529 MT7981_TYPE0_PIN(16, "SPI0_CLK"),
530 MT7981_TYPE0_PIN(17, "SPI0_MOSI"),
531 MT7981_TYPE0_PIN(18, "SPI0_MISO"),
532 MT7981_TYPE0_PIN(19, "SPI0_CS"),
533 MT7981_TYPE0_PIN(20, "SPI0_HOLD"),
534 MT7981_TYPE0_PIN(21, "SPI0_WP"),
535 MT7981_TYPE0_PIN(22, "SPI1_CLK"),
536 MT7981_TYPE0_PIN(23, "SPI1_MOSI"),
537 MT7981_TYPE0_PIN(24, "SPI1_MISO"),
538 MT7981_TYPE0_PIN(25, "SPI1_CS"),
539 MT7981_TYPE0_PIN(26, "SPI2_CLK"),
540 MT7981_TYPE0_PIN(27, "SPI2_MOSI"),
541 MT7981_TYPE0_PIN(28, "SPI2_MISO"),
542 MT7981_TYPE0_PIN(29, "SPI2_CS"),
543 MT7981_TYPE0_PIN(30, "SPI2_HOLD"),
544 MT7981_TYPE0_PIN(31, "SPI2_WP"),
545 MT7981_TYPE0_PIN(32, "UART0_RXD"),
546 MT7981_TYPE0_PIN(33, "UART0_TXD"),
547 MT7981_TYPE0_PIN(34, "PCIE_CLK_REQ"),
548 MT7981_TYPE0_PIN(35, "PCIE_WAKE_N"),
549 MT7981_TYPE0_PIN(36, "SMI_MDC"),
550 MT7981_TYPE0_PIN(37, "SMI_MDIO"),
551 MT7981_TYPE0_PIN(38, "GBE_INT"),
552 MT7981_TYPE0_PIN(39, "GBE_RESET"),
553 MT7981_TYPE1_PIN(40, "WF_DIG_RESETB"),
554 MT7981_TYPE1_PIN(41, "WF_CBA_RESETB"),
555 MT7981_TYPE1_PIN(42, "WF_XO_REQ"),
556 MT7981_TYPE1_PIN(43, "WF_TOP_CLK"),
557 MT7981_TYPE1_PIN(44, "WF_TOP_DATA"),
558 MT7981_TYPE1_PIN(45, "WF_HB1"),
559 MT7981_TYPE1_PIN(46, "WF_HB2"),
560 MT7981_TYPE1_PIN(47, "WF_HB3"),
561 MT7981_TYPE1_PIN(48, "WF_HB4"),
562 MT7981_TYPE1_PIN(49, "WF_HB0"),
563 MT7981_TYPE1_PIN(50, "WF_HB0_B"),
564 MT7981_TYPE1_PIN(51, "WF_HB5"),
565 MT7981_TYPE1_PIN(52, "WF_HB6"),
566 MT7981_TYPE1_PIN(53, "WF_HB7"),
567 MT7981_TYPE1_PIN(54, "WF_HB8"),
568 MT7981_TYPE1_PIN(55, "WF_HB9"),
569 MT7981_TYPE1_PIN(56, "WF_HB10"),
570};
571
572/* WA_AICE */
573static int mt7981_wa_aice1_pins[] = { 0, 1, };
574static int mt7981_wa_aice1_funcs[] = { 2, 2, };
575
576static int mt7981_wa_aice2_pins[] = { 0, 1, };
577static int mt7981_wa_aice2_funcs[] = { 3, 3, };
578
579static int mt7981_wa_aice3_pins[] = { 28, 29, };
580static int mt7981_wa_aice3_funcs[] = { 3, 3, };
581
582static int mt7981_wm_aice1_pins[] = { 9, 10, };
583static int mt7981_wm_aice1_funcs[] = { 2, 2, };
584
585static int mt7981_wm_aice2_pins[] = { 30, 31, };
586static int mt7981_wm_aice2_funcs[] = { 5, 5, };
587
588/* WM_UART */
589static int mt7981_wm_uart_0_pins[] = { 0, 1, };
590static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
591
592static int mt7981_wm_uart_1_pins[] = { 20, 21, };
593static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
594
595static int mt7981_wm_uart_2_pins[] = { 30, 31, };
596static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
597
598/* DFD */
599static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
600static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
601
602/* SYS_WATCHDOG */
603static int mt7981_watchdog_pins[] = { 2, };
604static int mt7981_watchdog_funcs[] = { 1, };
605
606static int mt7981_watchdog1_pins[] = { 13, };
607static int mt7981_watchdog1_funcs[] = { 5, };
608
609/* PCIE_PERESET_N */
610static int mt7981_pcie_pereset_pins[] = { 3, };
611static int mt7981_pcie_pereset_funcs[] = { 1, };
612
613/* JTAG */
614static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
615static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
616
617/* WM_JTAG */
618static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
619static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
620
621static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
622static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
623
624/* WO0_JTAG */
625static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
626static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
627
628static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
629static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
630
631/* UART2 */
632static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
633static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
634
635/* GBE_LED0 */
636static int mt7981_gbe_led0_pins[] = { 8, };
637static int mt7981_gbe_led0_funcs[] = { 3, };
638
639/* PTA_EXT */
640static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
641static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
642
643static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
644static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
645
646/* PWM2 */
647static int mt7981_pwm2_pins[] = { 7, };
648static int mt7981_pwm2_funcs[] = { 4, };
649
650/* NET_WO0_UART_TXD */
651static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
652static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
653
654static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
655static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
656
657static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
658static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
659
660/* SPI1 */
661static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
662static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
663
664/* I2C */
665static int mt7981_i2c0_0_pins[] = { 6, 7, };
666static int mt7981_i2c0_0_funcs[] = { 6, 6, };
667
668static int mt7981_i2c0_1_pins[] = { 30, 31, };
669static int mt7981_i2c0_1_funcs[] = { 4, 4, };
670
671static int mt7981_i2c0_2_pins[] = { 36, 37, };
672static int mt7981_i2c0_2_funcs[] = { 2, 2, };
673
674static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
675static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
676
677static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
678static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
679
680static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
681static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
682
683static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
684static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
685
686/* DFD_NTRST */
687static int mt7981_dfd_ntrst_pins[] = { 8, };
688static int mt7981_dfd_ntrst_funcs[] = { 6, };
689
690/* PWM0 */
691static int mt7981_pwm0_0_pins[] = { 13, };
692static int mt7981_pwm0_0_funcs[] = { 2, };
693
694static int mt7981_pwm0_1_pins[] = { 15, };
695static int mt7981_pwm0_1_funcs[] = { 1, };
696
697/* PWM1 */
698static int mt7981_pwm1_0_pins[] = { 14, };
699static int mt7981_pwm1_0_funcs[] = { 2, };
700
701static int mt7981_pwm1_1_pins[] = { 15, };
702static int mt7981_pwm1_1_funcs[] = { 3, };
703
704/* GBE_LED1 */
705static int mt7981_gbe_led1_pins[] = { 13, };
706static int mt7981_gbe_led1_funcs[] = { 3, };
707
708/* PCM */
709static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
710static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
711
712/* UDI */
713static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
714static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
715
716/* DRV_VBUS */
717static int mt7981_drv_vbus_pins[] = { 14, };
718static int mt7981_drv_vbus_funcs[] = { 1, };
719
720/* EMMC */
721static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
722static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
723
724/* SNFI */
725static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
726static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
727
728/* SPI0 */
729static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
730static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
731
732/* SPI0 */
733static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
734static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
735
736/* SPI1 */
737static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
738static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
739
740/* SPI2 */
741static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
742static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
743
744/* SPI2 */
745static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
746static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
747
748/* UART1 */
749static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
750static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
751
752static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
753static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
754
755/* UART2 */
756static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
757static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
758
759/* UART0 */
760static int mt7981_uart0_pins[] = { 32, 33, };
761static int mt7981_uart0_funcs[] = { 1, 1, };
762
763/* PCIE_CLK_REQ */
764static int mt7981_pcie_clk_pins[] = { 34, };
765static int mt7981_pcie_clk_funcs[] = { 2, };
766
767/* PCIE_WAKE_N */
768static int mt7981_pcie_wake_pins[] = { 35, };
769static int mt7981_pcie_wake_funcs[] = { 2, };
770
771/* MDC_MDIO */
772static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
773static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
774
775static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
776static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
777
778/* WF0_MODE1 */
779static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
780 50, 51, 52, 53, 54, 55, 56 };
781static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
782 1, 1, 1, 1 };
783
784/* WF0_MODE3 */
785static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
786static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
787
788/* WF2G_LED */
789static int mt7981_wf2g_led0_pins[] = { 30, };
790static int mt7981_wf2g_led0_funcs[] = { 2, };
791
792static int mt7981_wf2g_led1_pins[] = { 34, };
793static int mt7981_wf2g_led1_funcs[] = { 1, };
794
795/* WF5G_LED */
796static int mt7981_wf5g_led0_pins[] = { 31, };
797static int mt7981_wf5g_led0_funcs[] = { 2, };
798
799static int mt7981_wf5g_led1_pins[] = { 35, };
800static int mt7981_wf5g_led1_funcs[] = { 1, };
801
802/* MT7531_INT */
803static int mt7981_mt7531_int_pins[] = { 38, };
804static int mt7981_mt7531_int_funcs[] = { 1, };
805
806/* ANT_SEL */
807static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
808static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
809
810static const struct mtk_group_desc mt7981_groups[] = {
811 /* @GPIO(0,1): WA_AICE(2) */
812 PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
813 /* @GPIO(0,1): WA_AICE(3) */
814 PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
815 /* @GPIO(0,1): WM_UART(5) */
816 PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
817 /* @GPIO(0,1,4,5): DFD(6) */
818 PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
819 /* @GPIO(2): SYS_WATCHDOG(1) */
820 PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
821 /* @GPIO(3): PCIE_PERESET_N(1) */
822 PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
823 /* @GPIO(4,8) JTAG(1) */
824 PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
825 /* @GPIO(4,8) WM_JTAG(2) */
826 PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
827 /* @GPIO(9,13) WO0_JTAG(1) */
828 PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
829 /* @GPIO(4,7) WM_JTAG(3) */
830 PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
831 /* @GPIO(8) GBE_LED0(3) */
832 PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
833 /* @GPIO(4,6) PTA_EXT(4) */
834 PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
835 /* @GPIO(7) PWM2(4) */
836 PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
837 /* @GPIO(8) NET_WO0_UART_TXD(4) */
838 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
839 /* @GPIO(4,7) SPI1(5) */
840 PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
841 /* @GPIO(6,7) I2C(5) */
842 PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
843 /* @GPIO(8): DFD_NTRST(6) */
844 PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
845 /* @GPIO(9,10): WM_AICE(2) */
846 PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
847 /* @GPIO(13): PWM0(2) */
848 PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
849 /* @GPIO(15): PWM0(1) */
850 PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
851 /* @GPIO(14): PWM1(2) */
852 PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
853 /* @GPIO(15): PWM1(3) */
854 PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
855 /* @GPIO(14) NET_WO0_UART_TXD(3) */
856 PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
857 /* @GPIO(15) NET_WO0_UART_TXD(4) */
858 PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
859 /* @GPIO(13) GBE_LED0(3) */
860 PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
861 /* @GPIO(9,13) PCM(4) */
862 PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
863 /* @GPIO(13): SYS_WATCHDOG1(5) */
864 PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
865 /* @GPIO(9,13) UDI(4) */
866 PINCTRL_PIN_GROUP("udi", mt7981_udi),
867 /* @GPIO(14) DRV_VBUS(1) */
868 PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
869 /* @GPIO(15,25): EMMC(2) */
870 PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
871 /* @GPIO(16,21): SNFI(3) */
872 PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
873 /* @GPIO(16,19): SPI0(1) */
874 PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
875 /* @GPIO(20,21): SPI0(1) */
876 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
877 /* @GPIO(22,25) SPI1(1) */
878 PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
879 /* @GPIO(26,29): SPI2(1) */
880 PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
881 /* @GPIO(30,31): SPI2(1) */
882 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
883 /* @GPIO(16,19): UART1(4) */
884 PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
885 /* @GPIO(26,29): UART1(2) */
886 PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
887 /* @GPIO(22,25): UART2(3) */
888 PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1),
889 /* @GPIO(22,24) PTA_EXT(4) */
890 PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
891 /* @GPIO(20,21): WM_UART(4) */
892 PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
893 /* @GPIO(30,31): WM_UART(3) */
894 PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
895 /* @GPIO(20,24) WM_JTAG(5) */
896 PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
897 /* @GPIO(25,29) WO0_JTAG(5) */
898 PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
899 /* @GPIO(28,29): WA_AICE(3) */
900 PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
901 /* @GPIO(30,31): WM_AICE(5) */
902 PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
903 /* @GPIO(30,31): I2C(4) */
904 PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
905 /* @GPIO(30,31): I2C(6) */
906 PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
907 /* @GPIO(32,33): I2C(1) */
908 PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
909 /* @GPIO(32,33): I2C(2) */
910 PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
911 /* @GPIO(32,33): I2C(3) */
912 PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
913 /* @GPIO(32,33): I2C(5) */
914 PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
915 /* @GPIO(34): PCIE_CLK_REQ(2) */
916 PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
917 /* @GPIO(35): PCIE_WAKE_N(2) */
918 PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
919 /* @GPIO(36,37): I2C(2) */
920 PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
921 /* @GPIO(36,37): MDC_MDIO(1) */
922 PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
923 /* @GPIO(36,37): MDC_MDIO(3) */
924 PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
925 /* @GPIO(40,56): WF0_MODE1(1) */
926 PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
927 /* @GPIO(45,46,47,48,49,51): WF0_MODE3(3) */
928 PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
929 /* @GPIO(30): WF2G_LED(2) */
930 PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
931 /* @GPIO(34): WF2G_LED(1) */
932 PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
933 /* @GPIO(31): WF5G_LED(2) */
934 PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
935 /* @GPIO(35): WF5G_LED(1) */
936 PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
937 /* @GPIO(38): MT7531_INT(1) */
938 PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
939 /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
940 PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
941};
942
943static const struct mtk_io_type_desc mt7981_io_type_desc[] = {
944 [IO_TYPE_GRP0] = {
945 .name = "18OD33",
946 .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
947 .drive_set = mtk_pinconf_drive_set_v1,
948 .input_enable = mtk_pinconf_input_enable_v1,
949 },
950 [IO_TYPE_GRP1] = {
951 .name = "18A01",
952 .bias_set = mtk_pinconf_bias_set_pu_pd,
953 .drive_set = mtk_pinconf_drive_set_v1,
954 .input_enable = mtk_pinconf_input_enable_v1,
955 },
956};
957
958/* Joint those groups owning the same capability in user point of view which
959 * allows that people tend to use through the device tree.
960 */
961static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2",
962 "wm_aice1_1", "wa_aice3", "wm_aice1_2", };
963static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
964 "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
965 "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", };
966static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
967static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
968static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk",
969 "pcie_wake", };
970static const char *const mt7981_jtag_groups[] = { "jtag", "wm_jtag_0",
971 "wo0_jtag_0", "wo0_jtag_1", "wm_jtag_1", };
972static const char *const mt7981_led_groups[] = { "gbe_led0", "gbe_led1",
973 "wf2g_led0", "wf2g_led1", "wf5g_led0", "wf5g_led1", };
974static const char *const mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
975static const char *const mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
976 "pwm1_0", "pwm1_1", };
977static const char *const mt7981_spi_groups[] = { "spi1_0", "spi0",
978 "spi0_wp_hold", "spi1_1", "spi2", "spi2_wp_hold", };
979static const char *const mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1",
980 "u2_phy_i2c", "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c",
981 "i2c0_2", };
982static const char *const mt7981_pcm_groups[] = { "pcm", };
983static const char *const mt7981_udi_groups[] = { "udi", };
984static const char *const mt7981_usb_groups[] = { "drv_vbus", };
985static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", };
986static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio",
987 "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", };
988static const char *const mt7981_ant_groups[] = { "ant_sel", };
989
990static const struct mtk_function_desc mt7981_functions[] = {
991 {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
992 {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
993 {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
994 {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
995 {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
996 {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
997 {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
998 {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
999 {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
1000 {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
1001 {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
1002 {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
1003 {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
1004 {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
1005 {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
1006 {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
1007 {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
1008};
1009
1010static const char *const mt7981_pinctrl_register_base_names[] = {
1011 "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base",
1012 "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
1013};
1014
1015static struct mtk_pinctrl_soc mt7981_data = {
1016 .name = "mt7981_pinctrl",
1017 .reg_cal = mt7981_reg_cals,
1018 .pins = mt7981_pins,
1019 .npins = ARRAY_SIZE(mt7981_pins),
1020 .grps = mt7981_groups,
1021 .ngrps = ARRAY_SIZE(mt7981_groups),
1022 .funcs = mt7981_functions,
1023 .nfuncs = ARRAY_SIZE(mt7981_functions),
1024 .io_type = mt7981_io_type_desc,
1025 .ntype = ARRAY_SIZE(mt7981_io_type_desc),
1026 .gpio_mode = 0,
1027 .base_names = mt7981_pinctrl_register_base_names,
1028 .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
1029 .base_calc = 1,
1030};
1031
1032static int mtk_pinctrl_mt7981_probe(struct udevice *dev)
1033{
1034 return mtk_pinctrl_common_probe(dev, &mt7981_data);
1035}
1036
1037static const struct udevice_id mt7981_pctrl_match[] = {
1038 {.compatible = "mediatek,mt7981-pinctrl"},
1039 { /* sentinel */ }
1040};
1041
1042U_BOOT_DRIVER(mt7981_pinctrl) = {
1043 .name = "mt7981_pinctrl",
1044 .id = UCLASS_PINCTRL,
1045 .of_match = mt7981_pctrl_match,
1046 .ops = &mtk_pinctrl_ops,
1047 .probe = mtk_pinctrl_mt7981_probe,
1048 .priv_auto = sizeof(struct mtk_pinctrl_priv),
1049};