| Gilles Talis | 42a5635 | 2023-12-13 09:29:40 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * Copyright 2018-2019, 2021 NXP |
| 4 | * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #include <asm/arch/clock.h> |
| 8 | #include <asm/arch/ddr.h> |
| 9 | #include <asm/arch/imx8mp_pins.h> |
| 10 | #include <asm/arch/sys_proto.h> |
| 11 | #include <asm/global_data.h> |
| 12 | #include <asm/mach-imx/boot_mode.h> |
| 13 | #include <asm/sections.h> |
| Gilles Talis | 42a5635 | 2023-12-13 09:29:40 -0300 | [diff] [blame] | 14 | #include <dm/device.h> |
| 15 | #include <dm/uclass.h> |
| 16 | #include <hang.h> |
| 17 | #include <init.h> |
| 18 | #include <log.h> |
| 19 | #include <power/pca9450.h> |
| 20 | #include <power/pmic.h> |
| 21 | #include <spl.h> |
| 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
| 25 | int spl_board_boot_device(enum boot_device boot_dev_spl) |
| 26 | { |
| 27 | return BOOT_DEVICE_BOOTROM; |
| 28 | } |
| 29 | |
| 30 | void spl_dram_init(void) |
| 31 | { |
| 32 | ddr_init(&dram_timing); |
| 33 | } |
| 34 | |
| 35 | void spl_board_init(void) |
| 36 | { |
| 37 | /* |
| 38 | * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does |
| 39 | * not allow to change it. Should set the clock after PMIC |
| 40 | * setting done. Default is 400Mhz (system_pll1_800m with div = 2) |
| 41 | * set by ROM for ND VDD_SOC |
| 42 | */ |
| 43 | clock_enable(CCGR_GIC, 0); |
| 44 | clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); |
| 45 | clock_enable(CCGR_GIC, 1); |
| 46 | |
| 47 | puts("Normal Boot\n"); |
| 48 | } |
| 49 | |
| 50 | static int power_init_board(void) |
| 51 | { |
| 52 | struct udevice *dev; |
| 53 | int ret; |
| 54 | |
| 55 | ret = pmic_get("pmic@25", &dev); |
| 56 | if (ret == -ENODEV) { |
| 57 | puts("Failed to get PMIC\n"); |
| 58 | return 0; |
| 59 | } |
| 60 | if (ret != 0) |
| 61 | return ret; |
| 62 | |
| 63 | /* BUCKxOUT_DVS0/1 control BUCK123 output. */ |
| 64 | pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); |
| 65 | |
| 66 | /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ |
| 67 | if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) |
| 68 | /* Set DVS0 to 0.85V for special case. */ |
| 69 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); |
| 70 | else |
| 71 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); |
| 72 | |
| 73 | /* Set DVS1 to 0.85v for suspend. */ |
| 74 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); |
| 75 | |
| 76 | /* |
| 77 | * Enable DVS control through PMIC_STBY_REQ and |
| 78 | * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). |
| 79 | */ |
| 80 | pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); |
| 81 | |
| 82 | /* |
| 83 | * Kernel uses OD/OD frequency for SoC. |
| 84 | * To avoid timing risk from SoC to ARM, |
| 85 | * increase VDD_ARM to OD voltage 0.95V |
| 86 | */ |
| 87 | pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | int board_fit_config_name_match(const char *name) |
| 93 | { |
| 94 | if (is_imx8mp() && |
| 95 | !strcmp(name, "imx8mp-debix-model-a")) |
| 96 | return 0; |
| 97 | |
| 98 | return -1; |
| 99 | } |
| 100 | |
| 101 | void board_init_f(ulong dummy) |
| 102 | { |
| 103 | int ret; |
| 104 | |
| 105 | arch_cpu_init(); |
| 106 | |
| 107 | init_uart_clk(1); |
| 108 | |
| 109 | /* Clear the BSS. */ |
| 110 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 111 | |
| 112 | ret = spl_init(); |
| 113 | if (ret) { |
| 114 | debug("spl_init() failed: %d\n", ret); |
| 115 | hang(); |
| 116 | } |
| 117 | |
| 118 | preloader_console_init(); |
| 119 | |
| 120 | enable_tzc380(); |
| 121 | |
| 122 | power_init_board(); |
| 123 | |
| 124 | /* DDR initialization */ |
| 125 | spl_dram_init(); |
| 126 | |
| 127 | board_init_r(NULL, 0); |
| 128 | } |