| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/sound/fsl,spdif.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Shengjiu Wang <shengjiu.wang@nxp.com> |
| 11 | |
| 12 | description: | |
| 13 | The Freescale S/PDIF audio block is a stereo transceiver that allows the |
| 14 | processor to receive and transmit digital audio via an coaxial cable or |
| 15 | a fibre cable. |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | enum: |
| 20 | - fsl,imx35-spdif |
| 21 | - fsl,vf610-spdif |
| 22 | - fsl,imx6sx-spdif |
| 23 | - fsl,imx8qm-spdif |
| 24 | - fsl,imx8qxp-spdif |
| 25 | - fsl,imx8mq-spdif |
| 26 | - fsl,imx8mm-spdif |
| 27 | - fsl,imx8mn-spdif |
| 28 | - fsl,imx8ulp-spdif |
| 29 | |
| 30 | reg: |
| 31 | maxItems: 1 |
| 32 | |
| 33 | interrupts: |
| 34 | maxItems: 1 |
| 35 | |
| 36 | dmas: |
| 37 | items: |
| 38 | - description: DMA controller phandle and request line for RX |
| 39 | - description: DMA controller phandle and request line for TX |
| 40 | |
| 41 | dma-names: |
| 42 | items: |
| 43 | - const: rx |
| 44 | - const: tx |
| 45 | |
| 46 | clocks: |
| 47 | items: |
| 48 | - description: The core clock of spdif controller. |
| 49 | - description: Clock for tx0 and rx0. |
| 50 | - description: Clock for tx1 and rx1. |
| 51 | - description: Clock for tx2 and rx2. |
| 52 | - description: Clock for tx3 and rx3. |
| 53 | - description: Clock for tx4 and rx4. |
| 54 | - description: Clock for tx5 and rx5. |
| 55 | - description: Clock for tx6 and rx6. |
| 56 | - description: Clock for tx7 and rx7. |
| 57 | - description: The spba clock is required when SPDIF is placed as a bus |
| 58 | slave of the Shared Peripheral Bus and when two or more bus masters |
| 59 | (CPU, DMA or DSP) try to access it. This property is optional depending |
| 60 | on the SoC design. |
| 61 | - description: PLL clock source for 8kHz series rate, optional. |
| 62 | - description: PLL clock source for 11khz series rate, optional. |
| 63 | minItems: 9 |
| 64 | |
| 65 | clock-names: |
| 66 | items: |
| 67 | - const: core |
| 68 | - const: rxtx0 |
| 69 | - const: rxtx1 |
| 70 | - const: rxtx2 |
| 71 | - const: rxtx3 |
| 72 | - const: rxtx4 |
| 73 | - const: rxtx5 |
| 74 | - const: rxtx6 |
| 75 | - const: rxtx7 |
| 76 | - const: spba |
| 77 | - const: pll8k |
| 78 | - const: pll11k |
| 79 | minItems: 9 |
| 80 | |
| 81 | big-endian: |
| 82 | $ref: /schemas/types.yaml#/definitions/flag |
| 83 | description: | |
| 84 | If this property is absent, the native endian mode will be in use |
| 85 | as default, or the big endian mode will be in use for all the device |
| 86 | registers. Set this flag for HCDs with big endian descriptors and big |
| 87 | endian registers. |
| 88 | |
| 89 | required: |
| 90 | - compatible |
| 91 | - reg |
| 92 | - interrupts |
| 93 | - dmas |
| 94 | - dma-names |
| 95 | - clocks |
| 96 | - clock-names |
| 97 | |
| 98 | additionalProperties: false |
| 99 | |
| 100 | examples: |
| 101 | - | |
| 102 | spdif@2004000 { |
| 103 | compatible = "fsl,imx35-spdif"; |
| 104 | reg = <0x02004000 0x4000>; |
| 105 | interrupts = <0 52 0x04>; |
| 106 | dmas = <&sdma 14 18 0>, |
| 107 | <&sdma 15 18 0>; |
| 108 | dma-names = "rx", "tx"; |
| 109 | clocks = <&clks 197>, <&clks 3>, |
| 110 | <&clks 197>, <&clks 107>, |
| 111 | <&clks 0>, <&clks 118>, |
| 112 | <&clks 62>, <&clks 139>, |
| 113 | <&clks 0>; |
| 114 | clock-names = "core", "rxtx0", |
| 115 | "rxtx1", "rxtx2", |
| 116 | "rxtx3", "rxtx4", |
| 117 | "rxtx5", "rxtx6", |
| 118 | "rxtx7"; |
| 119 | big-endian; |
| 120 | }; |