| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Cadence PCIe Host |
| 8 | |
| 9 | maintainers: |
| 10 | - Tom Joseph <tjoseph@cadence.com> |
| 11 | |
| 12 | allOf: |
| 13 | - $ref: /schemas/pci/pci-bus.yaml# |
| 14 | - $ref: cdns-pcie.yaml# |
| 15 | |
| 16 | properties: |
| 17 | cdns,max-outbound-regions: |
| 18 | description: maximum number of outbound regions |
| 19 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 20 | minimum: 1 |
| 21 | maximum: 32 |
| 22 | default: 32 |
| 23 | deprecated: true |
| 24 | |
| 25 | cdns,no-bar-match-nbits: |
| 26 | description: |
| 27 | Set into the no BAR match register to configure the number of least |
| 28 | significant bits kept during inbound (PCIe -> AXI) address translations |
| 29 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 30 | minimum: 0 |
| 31 | maximum: 64 |
| 32 | default: 32 |
| 33 | deprecated: true |
| 34 | |
| 35 | msi-parent: true |
| 36 | |
| 37 | additionalProperties: true |