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git01.mediatek.com / filogic / uboot / 219e52c44cd21f75636527fc583d9fe9379792be / . / dts / upstream / Bindings / media / qcom,sdm660-venus.yaml
blob: a51835b220452efec7439c10eb253b08d2172209 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM660 Venus video encode and decode accelerators
8
9maintainers:
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
11 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
12
13description: |
14 The Venus IP is a video encode and decode accelerator present
15 on Qualcomm platforms
16
17allOf:
18 - $ref: qcom,venus-common.yaml#
19
20properties:
21 compatible:
22 const: qcom,sdm660-venus
23
24 clocks:
25 maxItems: 4
26
27 clock-names:
28 items:
29 - const: core
30 - const: iface
31 - const: bus
32 - const: bus_throttle
33
34 interconnects:
35 maxItems: 2
36
37 interconnect-names:
38 items:
39 - const: cpu-cfg
40 - const: video-mem
41
42 iommus:
43 maxItems: 20
44
45 power-domains:
46 maxItems: 1
47
48 video-decoder:
49 type: object
50
51 properties:
52 compatible:
53 const: venus-decoder
54
55 clocks:
56 maxItems: 1
57
58 clock-names:
59 items:
60 - const: vcodec0_core
61
62 power-domains:
63 maxItems: 1
64
65 required:
66 - compatible
67 - clocks
68 - clock-names
69 - power-domains
70
71 additionalProperties: false
72
73 video-encoder:
74 type: object
75
76 properties:
77 compatible:
78 const: venus-encoder
79
80 clocks:
81 maxItems: 1
82
83 clock-names:
84 items:
85 - const: vcodec0_core
86
87 power-domains:
88 maxItems: 1
89
90 required:
91 - compatible
92 - clocks
93 - clock-names
94 - power-domains
95
96 additionalProperties: false
97
98required:
99 - compatible
100 - iommus
101 - video-decoder
102 - video-encoder
103
104unevaluatedProperties: false
105
106examples:
107 - |
108 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
109 #include <dt-bindings/interrupt-controller/arm-gic.h>
110
111 video-codec@cc00000 {
112 compatible = "qcom,sdm660-venus";
113 reg = <0x0cc00000 0xff000>;
114 clocks = <&mmcc VIDEO_CORE_CLK>,
115 <&mmcc VIDEO_AHB_CLK>,
116 <&mmcc VIDEO_AXI_CLK>,
117 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
118 clock-names = "core", "iface", "bus", "bus_throttle";
119 interconnects = <&gnoc 0 &mnoc 13>,
120 <&mnoc 4 &bimc 5>;
121 interconnect-names = "cpu-cfg", "video-mem";
122 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
131 <&mmss_smmu 0x40b>,
132 <&mmss_smmu 0x40c>,
133 <&mmss_smmu 0x40d>,
134 <&mmss_smmu 0x410>,
135 <&mmss_smmu 0x421>,
136 <&mmss_smmu 0x428>,
137 <&mmss_smmu 0x429>,
138 <&mmss_smmu 0x42b>,
139 <&mmss_smmu 0x42c>,
140 <&mmss_smmu 0x42d>,
141 <&mmss_smmu 0x411>,
142 <&mmss_smmu 0x431>;
143 memory-region = <&venus_region>;
144 power-domains = <&mmcc VENUS_GDSC>;
145
146 video-decoder {
147 compatible = "venus-decoder";
148 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
149 clock-names = "vcodec0_core";
150 power-domains = <&mmcc VENUS_CORE0_GDSC>;
151 };
152
153 video-encoder {
154 compatible = "venus-encoder";
155 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
156 clock-names = "vcodec0_core";
157 power-domains = <&mmcc VENUS_CORE0_GDSC>;
158 };
159 };