| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Rockchip mailbox |
| 2 | |
| 3 | The Rockchip mailbox is used by the Rockchip CPU cores to communicate |
| 4 | requests to MCU processor. |
| 5 | |
| 6 | Refer to ./mailbox.txt for generic information about mailbox device-tree |
| 7 | bindings. |
| 8 | |
| 9 | Required properties: |
| 10 | |
| 11 | - compatible: should be one of the following. |
| 12 | - "rockchip,rk3368-mbox" for rk3368 |
| 13 | - reg: physical base address of the controller and length of memory mapped |
| 14 | region. |
| 15 | - interrupts: The interrupt number to the cpu. The interrupt specifier format |
| 16 | depends on the interrupt controller. |
| 17 | - #mbox-cells: Common mailbox binding property to identify the number |
| 18 | of cells required for the mailbox specifier. Should be 1 |
| 19 | |
| 20 | Example: |
| 21 | -------- |
| 22 | |
| 23 | /* RK3368 */ |
| 24 | mbox: mbox@ff6b0000 { |
| 25 | compatible = "rockchip,rk3368-mailbox"; |
| 26 | reg = <0x0 0xff6b0000 0x0 0x1000>, |
| 27 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 28 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| 29 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
| 30 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
| 31 | #mbox-cells = <1>; |
| 32 | }; |