blob: d9293c57f573c0534adb777f88efad95e5da6c85 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare APB I2C Controller
8
9maintainers:
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
11
12allOf:
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
15 properties:
16 compatible:
17 not:
18 contains:
19 const: mscc,ocelot-i2c
20 then:
21 properties:
22 reg:
23 maxItems: 1
24
25properties:
26 compatible:
27 oneOf:
28 - description: Generic Synopsys DesignWare I2C controller
29 const: snps,designware-i2c
30 - description: Microsemi Ocelot SoCs I2C controller
31 items:
32 - const: mscc,ocelot-i2c
33 - const: snps,designware-i2c
34 - description: Baikal-T1 SoC System I2C controller
35 const: baikal,bt1-sys-i2c
36
37 reg:
38 minItems: 1
39 items:
40 - description: DW APB I2C controller memory mapped registers
41 - description: |
42 ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
43 This registers are specific to the Ocelot I2C-controller.
44
45 interrupts:
46 maxItems: 1
47
48 clocks:
49 minItems: 1
50 items:
51 - description: I2C controller reference clock source
52 - description: APB interface clock source
53
54 clock-names:
55 minItems: 1
56 items:
57 - const: ref
58 - const: pclk
59
60 resets:
61 maxItems: 1
62
63 clock-frequency:
64 description: Desired I2C bus clock frequency in Hz
65 enum: [100000, 400000, 1000000, 3400000]
66 default: 400000
67
68 i2c-sda-hold-time-ns:
69 description: |
70 The property should contain the SDA hold time in nanoseconds. This option
71 is only supported in hardware blocks version 1.11a or newer or on
72 Microsemi SoCs.
73
74 i2c-scl-falling-time-ns:
75 description: |
76 The property should contain the SCL falling time in nanoseconds.
77 This value is used to compute the tLOW period.
78 default: 300
79
80 i2c-sda-falling-time-ns:
81 description: |
82 The property should contain the SDA falling time in nanoseconds.
83 This value is used to compute the tHIGH period.
84 default: 300
85
86 dmas:
87 items:
88 - description: TX DMA Channel
89 - description: RX DMA Channel
90
91 dma-names:
92 items:
93 - const: tx
94 - const: rx
95
96unevaluatedProperties: false
97
98required:
99 - compatible
100 - reg
101 - interrupts
102
103examples:
104 - |
105 i2c@f0000 {
106 compatible = "snps,designware-i2c";
107 reg = <0xf0000 0x1000>;
108 interrupts = <11>;
109 clock-frequency = <400000>;
110 };
111 - |
112 i2c@1120000 {
113 compatible = "snps,designware-i2c";
114 reg = <0x1120000 0x1000>;
115 interrupts = <12 1>;
116 clock-frequency = <400000>;
117 i2c-sda-hold-time-ns = <300>;
118 i2c-sda-falling-time-ns = <300>;
119 i2c-scl-falling-time-ns = <300>;
120 };
121 - |
122 i2c@2000 {
123 compatible = "snps,designware-i2c";
124 reg = <0x2000 0x100>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 clock-frequency = <400000>;
128 clocks = <&i2cclk>;
129 interrupts = <0>;
130
131 eeprom@64 {
132 compatible = "atmel,24c02";
133 reg = <0x64>;
134 };
135 };
136 - |
137 i2c@100400 {
138 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
139 reg = <0x100400 0x100>, <0x198 0x8>;
140 pinctrl-0 = <&i2c_pins>;
141 pinctrl-names = "default";
142 interrupts = <8>;
143 clocks = <&ahb_clk>;
144 };
145...