| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Allwinner A31 Dynamic Range Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Chen-Yu Tsai <wens@csie.org> |
| 11 | - Maxime Ripard <mripard@kernel.org> |
| 12 | |
| 13 | description: | |
| 14 | The DRC (Dynamic Range Controller) allows to dynamically adjust |
| 15 | pixel brightness/contrast based on histogram measurements for LCD |
| 16 | content adaptive backlight control. |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | enum: |
| 21 | - allwinner,sun6i-a31-drc |
| 22 | - allwinner,sun6i-a31s-drc |
| 23 | - allwinner,sun8i-a23-drc |
| 24 | - allwinner,sun8i-a33-drc |
| 25 | - allwinner,sun9i-a80-drc |
| 26 | |
| 27 | reg: |
| 28 | maxItems: 1 |
| 29 | |
| 30 | interrupts: |
| 31 | maxItems: 1 |
| 32 | |
| 33 | clocks: |
| 34 | items: |
| 35 | - description: The DRC interface clock |
| 36 | - description: The DRC module clock |
| 37 | - description: The DRC DRAM clock |
| 38 | |
| 39 | clock-names: |
| 40 | items: |
| 41 | - const: ahb |
| 42 | - const: mod |
| 43 | - const: ram |
| 44 | |
| 45 | resets: |
| 46 | maxItems: 1 |
| 47 | |
| 48 | ports: |
| 49 | $ref: /schemas/graph.yaml#/properties/ports |
| 50 | |
| 51 | properties: |
| 52 | port@0: |
| 53 | $ref: /schemas/graph.yaml#/properties/port |
| 54 | description: | |
| 55 | Input endpoints of the controller. |
| 56 | |
| 57 | port@1: |
| 58 | $ref: /schemas/graph.yaml#/properties/port |
| 59 | description: | |
| 60 | Output endpoints of the controller. |
| 61 | |
| 62 | required: |
| 63 | - port@0 |
| 64 | - port@1 |
| 65 | |
| 66 | required: |
| 67 | - compatible |
| 68 | - reg |
| 69 | - interrupts |
| 70 | - clocks |
| 71 | - clock-names |
| 72 | - resets |
| 73 | - ports |
| 74 | |
| 75 | additionalProperties: false |
| 76 | |
| 77 | examples: |
| 78 | - | |
| 79 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 80 | |
| 81 | #include <dt-bindings/clock/sun6i-a31-ccu.h> |
| 82 | #include <dt-bindings/reset/sun6i-a31-ccu.h> |
| 83 | |
| 84 | drc0: drc@1e70000 { |
| 85 | compatible = "allwinner,sun6i-a31-drc"; |
| 86 | reg = <0x01e70000 0x10000>; |
| 87 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 88 | clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, |
| 89 | <&ccu CLK_DRAM_DRC0>; |
| 90 | clock-names = "ahb", "mod", |
| 91 | "ram"; |
| 92 | resets = <&ccu RST_AHB1_DRC0>; |
| 93 | |
| 94 | ports { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | |
| 98 | drc0_in: port@0 { |
| 99 | reg = <0>; |
| 100 | |
| 101 | drc0_in_be0: endpoint { |
| 102 | remote-endpoint = <&be0_out_drc0>; |
| 103 | }; |
| 104 | }; |
| 105 | |
| 106 | drc0_out: port@1 { |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | reg = <1>; |
| 110 | |
| 111 | drc0_out_tcon0: endpoint@0 { |
| 112 | reg = <0>; |
| 113 | remote-endpoint = <&tcon0_in_drc0>; |
| 114 | }; |
| 115 | |
| 116 | drc0_out_tcon1: endpoint@1 { |
| 117 | reg = <1>; |
| 118 | remote-endpoint = <&tcon1_in_drc0>; |
| 119 | }; |
| 120 | }; |
| 121 | }; |
| 122 | }; |
| 123 | |
| 124 | |
| 125 | ... |