dts/upstream/Bindings/clock/hisilicon,hi3559av100-clock.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hisilicon SOC Clock for HI3559AV100

maintainers:
  - Dongjiu Geng <gengdongjiu@huawei.com>

description: |
  Hisilicon SOC clock control module which supports the clocks, resets and
  power domains on HI3559AV100.

  See also:
    dt-bindings/clock/hi3559av100-clock.h

properties:
  compatible:
    enum:
      - hisilicon,hi3559av100-clock
      - hisilicon,hi3559av100-shub-clock

  reg:
    minItems: 1
    maxItems: 2

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 2
    description: |
      First cell is reset request register offset.
      Second cell is bit offset in reset request register.

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        clock-controller@12010000 {
            compatible = "hisilicon,hi3559av100-clock";
            #clock-cells = <1>;
            #reset-cells = <2>;
            reg = <0x0 0x12010000 0x0 0x10000>;
        };
    };
...