blob: d8932ec26ca88527cfade55635c3b97a17e521ae [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic S4 PLL Clock Controller
9
10maintainers:
11 - Yu Tu <yu.tu@amlogic.com>
12
13properties:
14 compatible:
15 const: amlogic,s4-pll-clkc
16
17 reg:
18 maxItems: 1
19
20 clocks:
21 maxItems: 1
22
23 clock-names:
24 items:
25 - const: xtal
26
27 "#clock-cells":
28 const: 1
29
30required:
31 - compatible
32 - reg
33 - clocks
34 - clock-names
35 - "#clock-cells"
36
37additionalProperties: false
38
39examples:
40 - |
41 clkc_pll: clock-controller@fe008000 {
42 compatible = "amlogic,s4-pll-clkc";
43 reg = <0xfe008000 0x1e8>;
44 clocks = <&xtal>;
45 clock-names = "xtal";
46 #clock-cells = <1>;
47 };
48
49...