| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Broadcom BCM63138 DSL System-on-a-Chip device tree bindings |
| 2 | ----------------------------------------------------------- |
| 3 | |
| 4 | Boards compatible with the BCM63138 DSL System-on-a-Chip should have the |
| 5 | following properties: |
| 6 | |
| 7 | Required root node property: |
| 8 | |
| 9 | compatible: should be "brcm,bcm63138" |
| 10 | |
| 11 | An optional Boot lookup table Device Tree node is required for secondary CPU |
| 12 | initialization as well as a 'resets' phandle to the correct PMB controller as |
| 13 | defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an |
| 14 | 'enable-method' property. |
| 15 | |
| 16 | Required properties for the Boot lookup table node: |
| 17 | - compatible: should be "brcm,bcm63138-bootlut" |
| 18 | - reg: register base address and length for the Boot Lookup table |
| 19 | |
| 20 | Optional properties for the primary CPU node: |
| 21 | - enable-method: should be "brcm,bcm63138" |
| 22 | |
| 23 | Optional properties for the secondary CPU node: |
| 24 | - enable-method: should be "brcm,bcm63138" |
| 25 | - resets: phandle to the relevant PMB controller, one integer indicating the internal |
| 26 | bus number, and a second integer indicating the address of the CPU in the PMB |
| 27 | internal bus number. |
| 28 | |
| 29 | Example: |
| 30 | |
| 31 | cpus { |
| 32 | cpu@0 { |
| 33 | compatible = "arm,cortex-a9"; |
| 34 | reg = <0>; |
| 35 | ... |
| 36 | enable-method = "brcm,bcm63138"; |
| 37 | }; |
| 38 | |
| 39 | cpu@1 { |
| 40 | compatible = "arm,cortex-a9"; |
| 41 | reg = <1>; |
| 42 | ... |
| 43 | enable-method = "brcm,bcm63138"; |
| 44 | resets = <&pmb0 4 1>; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | bootlut: bootlut@8000 { |
| 49 | compatible = "brcm,bcm63138-bootlut"; |
| 50 | reg = <0x8000 0x50>; |
| 51 | }; |
| 52 | |
| 53 | ======= |
| 54 | reboot |
| 55 | ------ |
| 56 | Two nodes are required for software reboot: a timer node and a syscon-reboot node. |
| 57 | |
| 58 | Timer node: |
| 59 | |
| 60 | - compatible: Must be "brcm,bcm6328-timer", "syscon" |
| 61 | - reg: Register base address and length |
| 62 | |
| 63 | Syscon reboot node: |
| 64 | |
| 65 | See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the |
| 66 | detailed list of properties, the two values defined below are specific to the |
| 67 | BCM6328-style timer: |
| 68 | |
| 69 | - offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register |
| 70 | from the beginning of the TIMER block |
| 71 | - mask: Should be 1 for the SoftRst bit. |
| 72 | |
| 73 | Example: |
| 74 | |
| 75 | timer: timer@80 { |
| 76 | compatible = "brcm,bcm6328-timer", "syscon"; |
| 77 | reg = <0x80 0x3c>; |
| 78 | }; |
| 79 | |
| 80 | reboot { |
| 81 | compatible = "syscon-reboot"; |
| 82 | regmap = <&timer>; |
| 83 | offset = <0x34>; |
| 84 | mask = <0x1>; |
| 85 | }; |