blob: 5850e0c18c693941facbfc3a9b3ba90066a3c9e5 [file] [log] [blame]
Bin Mengc85a5be2018-10-15 02:21:23 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 *
5 * VirtIO PCI bus transport driver
6 * Ported from Linux drivers/virtio/virtio_pci*.c
7 */
8
Bin Mengc85a5be2018-10-15 02:21:23 -07009#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Bin Mengc85a5be2018-10-15 02:21:23 -070011#include <virtio_types.h>
12#include <virtio.h>
13#include <virtio_ring.h>
14#include <dm/device.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060015#include <linux/bug.h>
Bin Mengc85a5be2018-10-15 02:21:23 -070016#include <linux/compat.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070018#include <linux/err.h>
Bin Mengc85a5be2018-10-15 02:21:23 -070019#include <linux/io.h>
20#include "virtio_pci.h"
21
22#define VIRTIO_PCI_DRV_NAME "virtio-pci.m"
23
24/* PCI device ID in the range 0x1040 to 0x107f */
25#define VIRTIO_PCI_VENDOR_ID 0x1af4
26#define VIRTIO_PCI_DEVICE_ID00 0x1040
27#define VIRTIO_PCI_DEVICE_ID01 0x1041
28#define VIRTIO_PCI_DEVICE_ID02 0x1042
29#define VIRTIO_PCI_DEVICE_ID03 0x1043
30#define VIRTIO_PCI_DEVICE_ID04 0x1044
31#define VIRTIO_PCI_DEVICE_ID05 0x1045
32#define VIRTIO_PCI_DEVICE_ID06 0x1046
33#define VIRTIO_PCI_DEVICE_ID07 0x1047
34#define VIRTIO_PCI_DEVICE_ID08 0x1048
35#define VIRTIO_PCI_DEVICE_ID09 0x1049
36#define VIRTIO_PCI_DEVICE_ID0A 0x104a
37#define VIRTIO_PCI_DEVICE_ID0B 0x104b
38#define VIRTIO_PCI_DEVICE_ID0C 0x104c
39#define VIRTIO_PCI_DEVICE_ID0D 0x104d
40#define VIRTIO_PCI_DEVICE_ID0E 0x104e
41#define VIRTIO_PCI_DEVICE_ID0F 0x104f
42#define VIRTIO_PCI_DEVICE_ID10 0x1050
43#define VIRTIO_PCI_DEVICE_ID11 0x1051
44#define VIRTIO_PCI_DEVICE_ID12 0x1052
45#define VIRTIO_PCI_DEVICE_ID13 0x1053
46#define VIRTIO_PCI_DEVICE_ID14 0x1054
47#define VIRTIO_PCI_DEVICE_ID15 0x1055
48#define VIRTIO_PCI_DEVICE_ID16 0x1056
49#define VIRTIO_PCI_DEVICE_ID17 0x1057
50#define VIRTIO_PCI_DEVICE_ID18 0x1058
51#define VIRTIO_PCI_DEVICE_ID19 0x1059
52#define VIRTIO_PCI_DEVICE_ID1A 0x105a
53#define VIRTIO_PCI_DEVICE_ID1B 0x105b
54#define VIRTIO_PCI_DEVICE_ID1C 0x105c
55#define VIRTIO_PCI_DEVICE_ID1D 0x105d
56#define VIRTIO_PCI_DEVICE_ID1E 0x105e
57#define VIRTIO_PCI_DEVICE_ID1F 0x105f
58#define VIRTIO_PCI_DEVICE_ID20 0x1060
59#define VIRTIO_PCI_DEVICE_ID21 0x1061
60#define VIRTIO_PCI_DEVICE_ID22 0x1062
61#define VIRTIO_PCI_DEVICE_ID23 0x1063
62#define VIRTIO_PCI_DEVICE_ID24 0x1064
63#define VIRTIO_PCI_DEVICE_ID25 0x1065
64#define VIRTIO_PCI_DEVICE_ID26 0x1066
65#define VIRTIO_PCI_DEVICE_ID27 0x1067
66#define VIRTIO_PCI_DEVICE_ID28 0x1068
67#define VIRTIO_PCI_DEVICE_ID29 0x1069
68#define VIRTIO_PCI_DEVICE_ID2A 0x106a
69#define VIRTIO_PCI_DEVICE_ID2B 0x106b
70#define VIRTIO_PCI_DEVICE_ID2C 0x106c
71#define VIRTIO_PCI_DEVICE_ID2D 0x106d
72#define VIRTIO_PCI_DEVICE_ID2E 0x106e
73#define VIRTIO_PCI_DEVICE_ID2F 0x106f
74#define VIRTIO_PCI_DEVICE_ID30 0x1070
75#define VIRTIO_PCI_DEVICE_ID31 0x1071
76#define VIRTIO_PCI_DEVICE_ID32 0x1072
77#define VIRTIO_PCI_DEVICE_ID33 0x1073
78#define VIRTIO_PCI_DEVICE_ID34 0x1074
79#define VIRTIO_PCI_DEVICE_ID35 0x1075
80#define VIRTIO_PCI_DEVICE_ID36 0x1076
81#define VIRTIO_PCI_DEVICE_ID37 0x1077
82#define VIRTIO_PCI_DEVICE_ID38 0x1078
83#define VIRTIO_PCI_DEVICE_ID39 0x1079
84#define VIRTIO_PCI_DEVICE_ID3A 0x107a
85#define VIRTIO_PCI_DEVICE_ID3B 0x107b
86#define VIRTIO_PCI_DEVICE_ID3C 0x107c
87#define VIRTIO_PCI_DEVICE_ID3D 0x107d
88#define VIRTIO_PCI_DEVICE_ID3E 0x107e
89#define VIRTIO_PCI_DEVICE_ID3F 0x107f
90
91/**
92 * virtio pci transport driver private data
93 *
94 * @common: pci transport device common register block base
95 * @notify_base: pci transport device notify register block base
Andrew Scull5cda9c02022-04-21 16:11:02 +000096 * @notify_len: pci transport device notify register block length
Bin Mengc85a5be2018-10-15 02:21:23 -070097 * @device: pci transport device device-specific register block base
98 * @device_len: pci transport device device-specific register block length
99 * @notify_offset_multiplier: multiply queue_notify_off by this value
100 */
101struct virtio_pci_priv {
102 struct virtio_pci_common_cfg __iomem *common;
103 void __iomem *notify_base;
Andrew Scull5cda9c02022-04-21 16:11:02 +0000104 u32 notify_len;
Bin Mengc85a5be2018-10-15 02:21:23 -0700105 void __iomem *device;
106 u32 device_len;
107 u32 notify_offset_multiplier;
108};
109
110static int virtio_pci_get_config(struct udevice *udev, unsigned int offset,
111 void *buf, unsigned int len)
112{
113 struct virtio_pci_priv *priv = dev_get_priv(udev);
114 u8 b;
115 __le16 w;
116 __le32 l;
117
Andrew Sculla78d0562022-04-21 16:11:01 +0000118 if (!priv->device)
119 return -ENOSYS;
120
121 if (offset + len > priv->device_len)
122 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700123
124 switch (len) {
125 case 1:
126 b = ioread8(priv->device + offset);
127 memcpy(buf, &b, sizeof(b));
128 break;
129 case 2:
130 w = cpu_to_le16(ioread16(priv->device + offset));
131 memcpy(buf, &w, sizeof(w));
132 break;
133 case 4:
134 l = cpu_to_le32(ioread32(priv->device + offset));
135 memcpy(buf, &l, sizeof(l));
136 break;
137 case 8:
138 l = cpu_to_le32(ioread32(priv->device + offset));
139 memcpy(buf, &l, sizeof(l));
140 l = cpu_to_le32(ioread32(priv->device + offset + sizeof(l)));
141 memcpy(buf + sizeof(l), &l, sizeof(l));
142 break;
143 default:
Andrew Sculla78d0562022-04-21 16:11:01 +0000144 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700145 }
146
147 return 0;
148}
149
150static int virtio_pci_set_config(struct udevice *udev, unsigned int offset,
151 const void *buf, unsigned int len)
152{
153 struct virtio_pci_priv *priv = dev_get_priv(udev);
154 u8 b;
155 __le16 w;
156 __le32 l;
157
Andrew Sculla78d0562022-04-21 16:11:01 +0000158 if (!priv->device)
159 return -ENOSYS;
160
161 if (offset + len > priv->device_len)
162 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700163
164 switch (len) {
165 case 1:
166 memcpy(&b, buf, sizeof(b));
167 iowrite8(b, priv->device + offset);
168 break;
169 case 2:
170 memcpy(&w, buf, sizeof(w));
171 iowrite16(le16_to_cpu(w), priv->device + offset);
172 break;
173 case 4:
174 memcpy(&l, buf, sizeof(l));
175 iowrite32(le32_to_cpu(l), priv->device + offset);
176 break;
177 case 8:
178 memcpy(&l, buf, sizeof(l));
179 iowrite32(le32_to_cpu(l), priv->device + offset);
180 memcpy(&l, buf + sizeof(l), sizeof(l));
181 iowrite32(le32_to_cpu(l), priv->device + offset + sizeof(l));
182 break;
183 default:
Andrew Sculla78d0562022-04-21 16:11:01 +0000184 return -EINVAL;
Bin Mengc85a5be2018-10-15 02:21:23 -0700185 }
186
187 return 0;
188}
189
190static int virtio_pci_generation(struct udevice *udev, u32 *counter)
191{
192 struct virtio_pci_priv *priv = dev_get_priv(udev);
193
194 *counter = ioread8(&priv->common->config_generation);
195
196 return 0;
197}
198
199static int virtio_pci_get_status(struct udevice *udev, u8 *status)
200{
201 struct virtio_pci_priv *priv = dev_get_priv(udev);
202
203 *status = ioread8(&priv->common->device_status);
204
205 return 0;
206}
207
208static int virtio_pci_set_status(struct udevice *udev, u8 status)
209{
210 struct virtio_pci_priv *priv = dev_get_priv(udev);
211
212 /* We should never be setting status to 0 */
213 WARN_ON(status == 0);
214
215 iowrite8(status, &priv->common->device_status);
216
217 return 0;
218}
219
Bin Mengc85a5be2018-10-15 02:21:23 -0700220static int virtio_pci_get_features(struct udevice *udev, u64 *features)
221{
222 struct virtio_pci_priv *priv = dev_get_priv(udev);
223
224 iowrite32(0, &priv->common->device_feature_select);
225 *features = ioread32(&priv->common->device_feature);
226 iowrite32(1, &priv->common->device_feature_select);
227 *features |= ((u64)ioread32(&priv->common->device_feature) << 32);
228
229 return 0;
230}
231
232static int virtio_pci_set_features(struct udevice *udev)
233{
234 struct virtio_pci_priv *priv = dev_get_priv(udev);
235 struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
236
237 if (!__virtio_test_bit(udev, VIRTIO_F_VERSION_1)) {
238 debug("virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1\n");
239 return -EINVAL;
240 }
241
242 iowrite32(0, &priv->common->guest_feature_select);
243 iowrite32((u32)uc_priv->features, &priv->common->guest_feature);
244 iowrite32(1, &priv->common->guest_feature_select);
245 iowrite32(uc_priv->features >> 32, &priv->common->guest_feature);
246
247 return 0;
248}
249
250static struct virtqueue *virtio_pci_setup_vq(struct udevice *udev,
251 unsigned int index)
252{
253 struct virtio_pci_priv *priv = dev_get_priv(udev);
254 struct virtio_pci_common_cfg __iomem *cfg = priv->common;
255 struct virtqueue *vq;
256 u16 num;
257 u64 addr;
258 int err;
259
260 if (index >= ioread16(&cfg->num_queues))
261 return ERR_PTR(-ENOENT);
262
263 /* Select the queue we're interested in */
264 iowrite16(index, &cfg->queue_select);
265
266 /* Check if queue is either not available or already active */
267 num = ioread16(&cfg->queue_size);
268 if (!num || ioread16(&cfg->queue_enable))
269 return ERR_PTR(-ENOENT);
270
271 if (num & (num - 1)) {
272 printf("(%s): bad queue size %u", udev->name, num);
273 return ERR_PTR(-EINVAL);
274 }
275
276 /* Create the vring */
277 vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, udev);
278 if (!vq) {
279 err = -ENOMEM;
280 goto error_available;
281 }
282
283 /* Activate the queue */
284 iowrite16(virtqueue_get_vring_size(vq), &cfg->queue_size);
285
286 addr = virtqueue_get_desc_addr(vq);
287 iowrite32((u32)addr, &cfg->queue_desc_lo);
288 iowrite32(addr >> 32, &cfg->queue_desc_hi);
289
290 addr = virtqueue_get_avail_addr(vq);
291 iowrite32((u32)addr, &cfg->queue_avail_lo);
292 iowrite32(addr >> 32, &cfg->queue_avail_hi);
293
294 addr = virtqueue_get_used_addr(vq);
295 iowrite32((u32)addr, &cfg->queue_used_lo);
296 iowrite32(addr >> 32, &cfg->queue_used_hi);
297
298 iowrite16(1, &cfg->queue_enable);
299
300 return vq;
301
302error_available:
303 return ERR_PTR(err);
304}
305
306static void virtio_pci_del_vq(struct virtqueue *vq)
307{
308 struct virtio_pci_priv *priv = dev_get_priv(vq->vdev);
309 unsigned int index = vq->index;
310
311 iowrite16(index, &priv->common->queue_select);
312
313 /* Select and deactivate the queue */
314 iowrite16(0, &priv->common->queue_enable);
315
316 vring_del_virtqueue(vq);
317}
318
319static int virtio_pci_del_vqs(struct udevice *udev)
320{
321 struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
322 struct virtqueue *vq, *n;
323
324 list_for_each_entry_safe(vq, n, &uc_priv->vqs, list)
325 virtio_pci_del_vq(vq);
326
327 return 0;
328}
329
330static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs,
331 struct virtqueue *vqs[])
332{
333 int i;
334
335 for (i = 0; i < nvqs; ++i) {
336 vqs[i] = virtio_pci_setup_vq(udev, i);
337 if (IS_ERR(vqs[i])) {
338 virtio_pci_del_vqs(udev);
339 return PTR_ERR(vqs[i]);
340 }
341 }
342
343 return 0;
344}
345
Will Deacon46873ff2023-03-29 22:24:56 +0800346static int virtio_pci_reset(struct udevice *udev)
347{
348 struct virtio_pci_priv *priv = dev_get_priv(udev);
349
350 /* 0 status means a reset */
351 iowrite8(0, &priv->common->device_status);
352
353 /*
354 * After writing 0 to device_status, the driver MUST wait for a read
355 * of device_status to return 0 before reinitializing the device.
356 * This will flush out the status write, and flush in device writes,
357 * including MSI-X interrupts, if any.
358 */
359 while (ioread8(&priv->common->device_status))
360 udelay(1000);
361
362 return virtio_pci_del_vqs(udev);
363}
364
Bin Mengc85a5be2018-10-15 02:21:23 -0700365static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq)
366{
367 struct virtio_pci_priv *priv = dev_get_priv(udev);
368 u16 off;
369
370 /* Select the queue we're interested in */
371 iowrite16(vq->index, &priv->common->queue_select);
372
373 /* get offset of notification word for this vq */
374 off = ioread16(&priv->common->queue_notify_off);
375
376 /*
Andrew Scull5cda9c02022-04-21 16:11:02 +0000377 * Check the effective offset is in bounds and leaves space for the
378 * notification, which is just a single 16-bit value since
379 * VIRTIO_F_NOTIFICATION_DATA isn't negotiated by the drivers.
380 */
381 off *= priv->notify_offset_multiplier;
382 if (off > priv->notify_len - sizeof(u16))
383 return -EIO;
384
385 /*
Bin Mengc85a5be2018-10-15 02:21:23 -0700386 * We write the queue's selector into the notification register
387 * to signal the other end
388 */
Andrew Scull5cda9c02022-04-21 16:11:02 +0000389 iowrite16(vq->index, priv->notify_base + off);
Bin Mengc85a5be2018-10-15 02:21:23 -0700390
391 return 0;
392}
393
394/**
395 * virtio_pci_find_capability - walk capabilities to find device info
396 *
397 * @udev: the transport device
398 * @cfg_type: the VIRTIO_PCI_CAP_* value we seek
Andrew Scullf53c0572022-04-21 16:11:04 +0000399 * @cap_size: expected size of the capability
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000400 * @cap: capability read from the config space
Bin Mengc85a5be2018-10-15 02:21:23 -0700401 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100402 * Return: offset of the configuration structure
Bin Mengc85a5be2018-10-15 02:21:23 -0700403 */
Andrew Scullf53c0572022-04-21 16:11:04 +0000404static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000405 size_t cap_size,
406 struct virtio_pci_cap *cap)
Bin Mengc85a5be2018-10-15 02:21:23 -0700407{
408 int pos;
409 int offset;
Bin Mengc85a5be2018-10-15 02:21:23 -0700410
Andrew Scullf53c0572022-04-21 16:11:04 +0000411 assert(cap_size >= sizeof(struct virtio_pci_cap));
412 assert(cap_size <= PCI_CFG_SPACE_SIZE);
413
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000414 if (!cap)
415 return 0;
416
Bin Mengc85a5be2018-10-15 02:21:23 -0700417 for (pos = dm_pci_find_capability(udev, PCI_CAP_ID_VNDR);
418 pos > 0;
419 pos = dm_pci_find_next_capability(udev, pos, PCI_CAP_ID_VNDR)) {
Andrew Scullf53c0572022-04-21 16:11:04 +0000420 /* Ensure the capability is within bounds */
421 if (PCI_CFG_SPACE_SIZE - cap_size < pos)
422 return 0;
423
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000424 offset = pos + offsetof(struct virtio_pci_cap, cap_vndr);
425 dm_pci_read_config8(udev, offset, &cap->cap_vndr);
426 offset = pos + offsetof(struct virtio_pci_cap, cap_next);
427 dm_pci_read_config8(udev, offset, &cap->cap_next);
428 offset = pos + offsetof(struct virtio_pci_cap, cap_len);
429 dm_pci_read_config8(udev, offset, &cap->cap_len);
Bin Mengc85a5be2018-10-15 02:21:23 -0700430 offset = pos + offsetof(struct virtio_pci_cap, cfg_type);
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000431 dm_pci_read_config8(udev, offset, &cap->cfg_type);
Bin Mengc85a5be2018-10-15 02:21:23 -0700432 offset = pos + offsetof(struct virtio_pci_cap, bar);
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000433 dm_pci_read_config8(udev, offset, &cap->bar);
434 offset = pos + offsetof(struct virtio_pci_cap, offset);
435 dm_pci_read_config32(udev, offset, &cap->offset);
436 offset = pos + offsetof(struct virtio_pci_cap, length);
437 dm_pci_read_config32(udev, offset, &cap->length);
Bin Mengc85a5be2018-10-15 02:21:23 -0700438
439 /* Ignore structures with reserved BAR values */
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000440 if (cap->bar > 0x5)
Bin Mengc85a5be2018-10-15 02:21:23 -0700441 continue;
442
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000443 if (cap->cfg_type == cfg_type)
Bin Mengc85a5be2018-10-15 02:21:23 -0700444 return pos;
445 }
446
447 return 0;
448}
449
450/**
451 * virtio_pci_map_capability - map base address of the capability
452 *
453 * @udev: the transport device
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000454 * @cap: capability to map
Bin Mengc85a5be2018-10-15 02:21:23 -0700455 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100456 * Return: base address of the capability
Bin Mengc85a5be2018-10-15 02:21:23 -0700457 */
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000458static void __iomem *virtio_pci_map_capability(struct udevice *udev,
459 const struct virtio_pci_cap *cap)
Bin Mengc85a5be2018-10-15 02:21:23 -0700460{
Bin Mengc85a5be2018-10-15 02:21:23 -0700461 /*
Andrew Sculla625bbd2022-04-21 16:11:15 +0000462 * Find the corresponding memory region that isn't system memory but is
463 * writable.
Bin Mengc85a5be2018-10-15 02:21:23 -0700464 */
Andrew Sculla625bbd2022-04-21 16:11:15 +0000465 unsigned long mask =
466 PCI_REGION_TYPE | PCI_REGION_SYS_MEMORY | PCI_REGION_RO;
467 unsigned long flags = PCI_REGION_MEM;
Xiang Wba650ed2022-08-29 07:53:15 +0800468 u8 *p = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0 + 4 * cap->bar, cap->offset,
Andrew Sculla625bbd2022-04-21 16:11:15 +0000469 cap->length, mask, flags);
Bin Mengc85a5be2018-10-15 02:21:23 -0700470
Andrew Sculla625bbd2022-04-21 16:11:15 +0000471 return (void __iomem *)p;
Bin Mengc85a5be2018-10-15 02:21:23 -0700472}
473
474static int virtio_pci_bind(struct udevice *udev)
475{
476 static int num_devs;
477 char name[20];
478
479 /* Create a unique device name */
480 sprintf(name, "%s#%u", VIRTIO_PCI_DRV_NAME, num_devs++);
481 device_set_name(udev, name);
482
483 return 0;
484}
485
486static int virtio_pci_probe(struct udevice *udev)
487{
Simon Glassb75b15b2020-12-03 16:55:23 -0700488 struct pci_child_plat *pplat = dev_get_parent_plat(udev);
Bin Mengc85a5be2018-10-15 02:21:23 -0700489 struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
490 struct virtio_pci_priv *priv = dev_get_priv(udev);
491 u16 subvendor;
492 u8 revision;
493 int common, notify, device;
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000494 struct virtio_pci_cap common_cap, notify_cap, device_cap;
Bin Mengc85a5be2018-10-15 02:21:23 -0700495 int offset;
496
497 /* We only own devices >= 0x1040 and <= 0x107f: leave the rest. */
498 if (pplat->device < 0x1040 || pplat->device > 0x107f)
499 return -ENODEV;
500
501 /* Transitional devices must not have a PCI revision ID of 0 */
502 dm_pci_read_config8(udev, PCI_REVISION_ID, &revision);
503
504 /* Modern devices: simply use PCI device id, but start from 0x1040. */
505 uc_priv->device = pplat->device - 0x1040;
506 dm_pci_read_config16(udev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor);
507 uc_priv->vendor = subvendor;
508
509 /* Check for a common config: if not, use legacy mode (bar 0) */
Andrew Scullf53c0572022-04-21 16:11:04 +0000510 common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000511 sizeof(struct virtio_pci_cap),
512 &common_cap);
Bin Mengc85a5be2018-10-15 02:21:23 -0700513 if (!common) {
514 printf("(%s): leaving for legacy driver\n", udev->name);
515 return -ENODEV;
516 }
517
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000518 if (common_cap.length < sizeof(struct virtio_pci_common_cfg)) {
Andrew Scull53d6e1d2022-04-21 16:11:03 +0000519 printf("(%s): virtio common config too small\n", udev->name);
520 return -EINVAL;
521 }
522
Bin Mengc85a5be2018-10-15 02:21:23 -0700523 /* If common is there, notify should be too */
Andrew Scullf53c0572022-04-21 16:11:04 +0000524 notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000525 sizeof(struct virtio_pci_notify_cap),
526 &notify_cap);
Bin Mengc85a5be2018-10-15 02:21:23 -0700527 if (!notify) {
528 printf("(%s): missing capabilities %i/%i\n", udev->name,
529 common, notify);
530 return -EINVAL;
531 }
532
Andrew Scull3d41dd42022-04-21 16:11:14 +0000533 /* Map configuration structures */
534 priv->common = virtio_pci_map_capability(udev, &common_cap);
535 if (!priv->common) {
536 printf("(%s): could not map common config\n", udev->name);
537 return -EINVAL;
538 }
539
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000540 priv->notify_len = notify_cap.length;
Andrew Scull3d41dd42022-04-21 16:11:14 +0000541 priv->notify_base = virtio_pci_map_capability(udev, &notify_cap);
542 if (!priv->notify_base) {
543 printf("(%s): could not map notify config\n", udev->name);
544 return -EINVAL;
545 }
Andrew Scull5cda9c02022-04-21 16:11:02 +0000546
Bin Mengc85a5be2018-10-15 02:21:23 -0700547 /*
548 * Device capability is only mandatory for devices that have
549 * device-specific configuration.
550 */
Andrew Scullf53c0572022-04-21 16:11:04 +0000551 device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG,
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000552 sizeof(struct virtio_pci_cap),
553 &device_cap);
Bin Mengc85a5be2018-10-15 02:21:23 -0700554 if (device) {
Andrew Sculld1cc2b52022-04-21 16:11:05 +0000555 priv->device_len = device_cap.length;
556 priv->device = virtio_pci_map_capability(udev, &device_cap);
Andrew Scull3d41dd42022-04-21 16:11:14 +0000557 if (!priv->device) {
558 printf("(%s): could not map device config\n",
559 udev->name);
560 return -EINVAL;
561 }
Bin Mengc85a5be2018-10-15 02:21:23 -0700562 }
563
Bin Mengc85a5be2018-10-15 02:21:23 -0700564 debug("(%p): common @ %p, notify base @ %p, device @ %p\n",
565 udev, priv->common, priv->notify_base, priv->device);
566
567 /* Read notify_off_multiplier from config space */
568 offset = notify + offsetof(struct virtio_pci_notify_cap,
569 notify_off_multiplier);
570 dm_pci_read_config32(udev, offset, &priv->notify_offset_multiplier);
571
572 debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name,
573 uc_priv->device, uc_priv->vendor, revision);
574
575 return 0;
576}
577
578static const struct dm_virtio_ops virtio_pci_ops = {
579 .get_config = virtio_pci_get_config,
580 .set_config = virtio_pci_set_config,
581 .generation = virtio_pci_generation,
582 .get_status = virtio_pci_get_status,
583 .set_status = virtio_pci_set_status,
584 .reset = virtio_pci_reset,
585 .get_features = virtio_pci_get_features,
586 .set_features = virtio_pci_set_features,
587 .find_vqs = virtio_pci_find_vqs,
588 .del_vqs = virtio_pci_del_vqs,
589 .notify = virtio_pci_notify,
590};
591
592U_BOOT_DRIVER(virtio_pci_modern) = {
593 .name = VIRTIO_PCI_DRV_NAME,
594 .id = UCLASS_VIRTIO,
595 .ops = &virtio_pci_ops,
596 .bind = virtio_pci_bind,
597 .probe = virtio_pci_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700598 .priv_auto = sizeof(struct virtio_pci_priv),
Bin Mengc85a5be2018-10-15 02:21:23 -0700599};
600
601static struct pci_device_id virtio_pci_supported[] = {
602 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID00) },
603 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID01) },
604 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID02) },
605 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID03) },
606 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID04) },
607 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID05) },
608 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID06) },
609 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID07) },
610 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID08) },
611 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID09) },
612 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0A) },
613 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0B) },
614 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0C) },
615 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0D) },
616 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0E) },
617 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0F) },
618 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID10) },
619 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID11) },
620 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID12) },
621 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID13) },
622 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID14) },
623 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID15) },
624 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID16) },
625 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID17) },
626 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID18) },
627 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID19) },
628 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1A) },
629 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1B) },
630 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1C) },
631 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1D) },
632 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1E) },
633 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1F) },
634 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID20) },
635 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID21) },
636 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID22) },
637 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID23) },
638 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID24) },
639 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID25) },
640 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID26) },
641 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID27) },
642 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID28) },
643 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID29) },
644 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2A) },
645 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2B) },
646 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2C) },
647 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2D) },
648 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2E) },
649 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2F) },
650 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID30) },
651 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID31) },
652 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID32) },
653 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID33) },
654 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID34) },
655 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID35) },
656 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID36) },
657 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID37) },
658 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID38) },
659 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID39) },
660 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3A) },
661 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3B) },
662 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3C) },
663 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3D) },
664 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3E) },
665 { PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3F) },
666 {},
667};
668
669U_BOOT_PCI_DEVICE(virtio_pci_modern, virtio_pci_supported);