Svyatoslav Ryhel | ef1e26b | 2024-01-31 08:57:17 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2020 Texas Instruments Incorporated |
| 4 | * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #include <clk.h> |
| 8 | #include <dm.h> |
| 9 | #include <i2c.h> |
| 10 | #include <log.h> |
| 11 | #include <mipi_display.h> |
| 12 | #include <mipi_dsi.h> |
| 13 | #include <backlight.h> |
| 14 | #include <panel.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/math64.h> |
| 19 | #include <power/regulator.h> |
| 20 | |
| 21 | #include <asm/gpio.h> |
| 22 | |
| 23 | /* Global (16-bit addressable) */ |
| 24 | #define TC358768_CHIPID 0x0000 |
| 25 | #define TC358768_SYSCTL 0x0002 |
| 26 | #define TC358768_CONFCTL 0x0004 |
| 27 | #define TC358768_VSDLY 0x0006 |
| 28 | #define TC358768_DATAFMT 0x0008 |
| 29 | #define TC358768_GPIOEN 0x000E |
| 30 | #define TC358768_GPIODIR 0x0010 |
| 31 | #define TC358768_GPIOIN 0x0012 |
| 32 | #define TC358768_GPIOOUT 0x0014 |
| 33 | #define TC358768_PLLCTL0 0x0016 |
| 34 | #define TC358768_PLLCTL1 0x0018 |
| 35 | #define TC358768_CMDBYTE 0x0022 |
| 36 | #define TC358768_PP_MISC 0x0032 |
| 37 | #define TC358768_DSITX_DT 0x0050 |
| 38 | #define TC358768_FIFOSTATUS 0x00F8 |
| 39 | |
| 40 | /* Debug (16-bit addressable) */ |
| 41 | #define TC358768_VBUFCTRL 0x00E0 |
| 42 | #define TC358768_DBG_WIDTH 0x00E2 |
| 43 | #define TC358768_DBG_VBLANK 0x00E4 |
| 44 | #define TC358768_DBG_DATA 0x00E8 |
| 45 | |
| 46 | /* TX PHY (32-bit addressable) */ |
| 47 | #define TC358768_CLW_DPHYCONTTX 0x0100 |
| 48 | #define TC358768_D0W_DPHYCONTTX 0x0104 |
| 49 | #define TC358768_D1W_DPHYCONTTX 0x0108 |
| 50 | #define TC358768_D2W_DPHYCONTTX 0x010C |
| 51 | #define TC358768_D3W_DPHYCONTTX 0x0110 |
| 52 | #define TC358768_CLW_CNTRL 0x0140 |
| 53 | #define TC358768_D0W_CNTRL 0x0144 |
| 54 | #define TC358768_D1W_CNTRL 0x0148 |
| 55 | #define TC358768_D2W_CNTRL 0x014C |
| 56 | #define TC358768_D3W_CNTRL 0x0150 |
| 57 | |
| 58 | /* TX PPI (32-bit addressable) */ |
| 59 | #define TC358768_STARTCNTRL 0x0204 |
| 60 | #define TC358768_DSITXSTATUS 0x0208 |
| 61 | #define TC358768_LINEINITCNT 0x0210 |
| 62 | #define TC358768_LPTXTIMECNT 0x0214 |
| 63 | #define TC358768_TCLK_HEADERCNT 0x0218 |
| 64 | #define TC358768_TCLK_TRAILCNT 0x021C |
| 65 | #define TC358768_THS_HEADERCNT 0x0220 |
| 66 | #define TC358768_TWAKEUP 0x0224 |
| 67 | #define TC358768_TCLK_POSTCNT 0x0228 |
| 68 | #define TC358768_THS_TRAILCNT 0x022C |
| 69 | #define TC358768_HSTXVREGCNT 0x0230 |
| 70 | #define TC358768_HSTXVREGEN 0x0234 |
| 71 | #define TC358768_TXOPTIONCNTRL 0x0238 |
| 72 | #define TC358768_BTACNTRL1 0x023C |
| 73 | |
| 74 | /* TX CTRL (32-bit addressable) */ |
| 75 | #define TC358768_DSI_CONTROL 0x040C |
| 76 | #define TC358768_DSI_STATUS 0x0410 |
| 77 | #define TC358768_DSI_INT 0x0414 |
| 78 | #define TC358768_DSI_INT_ENA 0x0418 |
| 79 | #define TC358768_DSICMD_RDFIFO 0x0430 |
| 80 | #define TC358768_DSI_ACKERR 0x0434 |
| 81 | #define TC358768_DSI_ACKERR_INTENA 0x0438 |
| 82 | #define TC358768_DSI_ACKERR_HALT 0x043c |
| 83 | #define TC358768_DSI_RXERR 0x0440 |
| 84 | #define TC358768_DSI_RXERR_INTENA 0x0444 |
| 85 | #define TC358768_DSI_RXERR_HALT 0x0448 |
| 86 | #define TC358768_DSI_ERR 0x044C |
| 87 | #define TC358768_DSI_ERR_INTENA 0x0450 |
| 88 | #define TC358768_DSI_ERR_HALT 0x0454 |
| 89 | #define TC358768_DSI_CONFW 0x0500 |
| 90 | #define TC358768_DSI_LPCMD 0x0500 |
| 91 | #define TC358768_DSI_RESET 0x0504 |
| 92 | #define TC358768_DSI_INT_CLR 0x050C |
| 93 | #define TC358768_DSI_START 0x0518 |
| 94 | |
| 95 | /* DSITX CTRL (16-bit addressable) */ |
| 96 | #define TC358768_DSICMD_TX 0x0600 |
| 97 | #define TC358768_DSICMD_TYPE 0x0602 |
| 98 | #define TC358768_DSICMD_WC 0x0604 |
| 99 | #define TC358768_DSICMD_WD0 0x0610 |
| 100 | #define TC358768_DSICMD_WD1 0x0612 |
| 101 | #define TC358768_DSICMD_WD2 0x0614 |
| 102 | #define TC358768_DSICMD_WD3 0x0616 |
| 103 | #define TC358768_DSI_EVENT 0x0620 |
| 104 | #define TC358768_DSI_VSW 0x0622 |
| 105 | #define TC358768_DSI_VBPR 0x0624 |
| 106 | #define TC358768_DSI_VACT 0x0626 |
| 107 | #define TC358768_DSI_HSW 0x0628 |
| 108 | #define TC358768_DSI_HBPR 0x062A |
| 109 | #define TC358768_DSI_HACT 0x062C |
| 110 | |
| 111 | /* TC358768_DSI_CONTROL (0x040C) register */ |
| 112 | #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) |
| 113 | #define TC358768_DSI_CONTROL_TXMD BIT(7) |
| 114 | #define TC358768_DSI_CONTROL_HSCKMD BIT(5) |
| 115 | #define TC358768_DSI_CONTROL_EOTDIS BIT(0) |
| 116 | |
| 117 | /* TC358768_DSI_CONFW (0x0500) register */ |
| 118 | #define TC358768_DSI_CONFW_MODE_SET (5 << 29) |
| 119 | #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) |
| 120 | #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (3 << 24) |
| 121 | |
| 122 | #define NANO 1000000000UL |
| 123 | #define PICO 1000000000000ULL |
| 124 | |
| 125 | struct tc358768_priv { |
| 126 | struct mipi_dsi_host host; |
| 127 | struct mipi_dsi_device device; |
| 128 | |
| 129 | struct udevice *panel; |
| 130 | struct display_timing timing; |
| 131 | |
| 132 | struct udevice *vddc; |
| 133 | struct udevice *vddmipi; |
| 134 | struct udevice *vddio; |
| 135 | |
| 136 | struct clk *refclk; |
| 137 | |
| 138 | struct gpio_desc reset_gpio; |
| 139 | |
| 140 | u32 pd_lines; /* number of Parallel Port Input Data Lines */ |
| 141 | u32 dsi_lanes; /* number of DSI Lanes */ |
| 142 | |
| 143 | /* Parameters for PLL programming */ |
| 144 | u32 fbd; /* PLL feedback divider */ |
| 145 | u32 prd; /* PLL input divider */ |
| 146 | u32 frs; /* PLL Freqency range for HSCK (post divider) */ |
| 147 | |
| 148 | u32 dsiclk; /* pll_clk / 2 */ |
| 149 | }; |
| 150 | |
| 151 | static void tc358768_read(struct udevice *dev, u32 reg, u32 *val) |
| 152 | { |
| 153 | int count; |
| 154 | u8 buf[4] = { 0, 0, 0, 0 }; |
| 155 | |
| 156 | /* 16-bit register? */ |
| 157 | if (reg < 0x100 || reg >= 0x600) |
| 158 | count = 2; |
| 159 | else |
| 160 | count = 4; |
| 161 | |
| 162 | dm_i2c_read(dev, reg, buf, count); |
| 163 | *val = (buf[0] << 8) | (buf[1] & 0xff) | |
| 164 | (buf[2] << 24) | (buf[3] << 16); |
| 165 | |
| 166 | log_debug("%s 0x%04x >> 0x%08x\n", |
| 167 | __func__, reg, *val); |
| 168 | } |
| 169 | |
| 170 | static void tc358768_write(struct udevice *dev, u32 reg, u32 val) |
| 171 | { |
| 172 | int count; |
| 173 | u8 buf[4]; |
| 174 | |
| 175 | /* 16-bit register? */ |
| 176 | if (reg < 0x100 || reg >= 0x600) |
| 177 | count = 2; |
| 178 | else |
| 179 | count = 4; |
| 180 | |
| 181 | buf[0] = val >> 8; |
| 182 | buf[1] = val & 0xff; |
| 183 | buf[2] = val >> 24; |
| 184 | buf[3] = val >> 16; |
| 185 | |
| 186 | log_debug("%s 0x%04x << 0x%08x\n", |
| 187 | __func__, reg, val); |
| 188 | |
| 189 | dm_i2c_write(dev, reg, buf, count); |
| 190 | } |
| 191 | |
| 192 | static void tc358768_update_bits(struct udevice *dev, u32 reg, u32 mask, |
| 193 | u32 val) |
| 194 | { |
| 195 | u32 tmp, orig; |
| 196 | |
| 197 | tc358768_read(dev, reg, &orig); |
| 198 | |
| 199 | tmp = orig & ~mask; |
| 200 | tmp |= val & mask; |
| 201 | if (tmp != orig) |
| 202 | tc358768_write(dev, reg, tmp); |
| 203 | } |
| 204 | |
| 205 | static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, |
| 206 | const struct mipi_dsi_msg *msg) |
| 207 | { |
| 208 | struct udevice *dev = (struct udevice *)host->dev; |
| 209 | struct mipi_dsi_packet packet; |
| 210 | int ret; |
| 211 | |
| 212 | if (msg->rx_len) { |
| 213 | log_debug("%s: MIPI rx is not supported\n", __func__); |
| 214 | return -EOPNOTSUPP; |
| 215 | } |
| 216 | |
| 217 | if (msg->tx_len > 8) { |
| 218 | log_debug("%s: Maximum 8 byte MIPI tx is supported\n", __func__); |
| 219 | return -EOPNOTSUPP; |
| 220 | } |
| 221 | |
| 222 | ret = mipi_dsi_create_packet(&packet, msg); |
| 223 | if (ret) |
| 224 | return ret; |
| 225 | |
| 226 | if (mipi_dsi_packet_format_is_short(msg->type)) { |
| 227 | tc358768_write(dev, TC358768_DSICMD_TYPE, |
| 228 | (0x10 << 8) | (packet.header[0] & 0x3f)); |
| 229 | tc358768_write(dev, TC358768_DSICMD_WC, 0); |
| 230 | tc358768_write(dev, TC358768_DSICMD_WD0, |
| 231 | (packet.header[2] << 8) | packet.header[1]); |
| 232 | } else { |
| 233 | int i; |
| 234 | |
| 235 | tc358768_write(dev, TC358768_DSICMD_TYPE, |
| 236 | (0x40 << 8) | (packet.header[0] & 0x3f)); |
| 237 | tc358768_write(dev, TC358768_DSICMD_WC, packet.payload_length); |
| 238 | for (i = 0; i < packet.payload_length; i += 2) { |
| 239 | u16 val = packet.payload[i]; |
| 240 | |
| 241 | if (i + 1 < packet.payload_length) |
| 242 | val |= packet.payload[i + 1] << 8; |
| 243 | |
| 244 | tc358768_write(dev, TC358768_DSICMD_WD0 + i, val); |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | /* start transfer */ |
| 249 | tc358768_write(dev, TC358768_DSICMD_TX, 1); |
| 250 | |
| 251 | return packet.size; |
| 252 | } |
| 253 | |
| 254 | static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { |
| 255 | .transfer = tc358768_dsi_host_transfer, |
| 256 | }; |
| 257 | |
| 258 | static void tc358768_sw_reset(struct udevice *dev) |
| 259 | { |
| 260 | /* Assert Reset */ |
| 261 | tc358768_write(dev, TC358768_SYSCTL, 1); |
| 262 | mdelay(5); |
| 263 | |
| 264 | /* Release Reset, Exit Sleep */ |
| 265 | tc358768_write(dev, TC358768_SYSCTL, 0); |
| 266 | } |
| 267 | |
| 268 | static void tc358768_hw_enable(struct tc358768_priv *priv) |
| 269 | { |
| 270 | int ret; |
| 271 | |
| 272 | ret = clk_prepare_enable(priv->refclk); |
| 273 | if (ret) |
| 274 | log_debug("%s: error enabling refclk (%d)\n", __func__, ret); |
| 275 | |
| 276 | ret = regulator_set_enable_if_allowed(priv->vddc, true); |
| 277 | if (ret) |
| 278 | log_debug("%s: error enabling vddc (%d)\n", __func__, ret); |
| 279 | |
| 280 | ret = regulator_set_enable_if_allowed(priv->vddmipi, true); |
| 281 | if (ret) |
| 282 | log_debug("%s: error enabling vddmipi (%d)\n", __func__, ret); |
| 283 | |
| 284 | mdelay(10); |
| 285 | |
| 286 | ret = regulator_set_enable_if_allowed(priv->vddio, true); |
| 287 | if (ret) |
| 288 | log_debug("%s: error enabling vddio (%d)\n", __func__, ret); |
| 289 | |
| 290 | mdelay(2); |
| 291 | |
| 292 | /* |
| 293 | * The RESX is active low (GPIO_ACTIVE_LOW). |
| 294 | * DEASSERT (value = 0) the reset_gpio to enable the chip |
| 295 | */ |
| 296 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 297 | if (ret) |
| 298 | log_debug("%s: error changing reset-gpio (%d)\n", __func__, ret); |
| 299 | |
| 300 | /* wait for encoder clocks to stabilize */ |
| 301 | mdelay(2); |
| 302 | } |
| 303 | |
| 304 | static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) |
| 305 | { |
| 306 | return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes); |
| 307 | } |
| 308 | |
| 309 | static int tc358768_calc_pll(struct tc358768_priv *priv, |
| 310 | struct display_timing *dt) |
| 311 | { |
| 312 | static const u32 frs_limits[] = { |
| 313 | 1000000000, |
| 314 | 500000000, |
| 315 | 250000000, |
| 316 | 125000000, |
| 317 | 62500000 |
| 318 | }; |
| 319 | unsigned long refclk; |
| 320 | u32 prd, target_pll, i, max_pll, min_pll; |
| 321 | u32 frs, best_diff, best_pll, best_prd, best_fbd; |
| 322 | |
| 323 | target_pll = tc358768_pclk_to_pll(priv, dt->pixelclock.typ); |
| 324 | |
| 325 | /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ |
| 326 | |
| 327 | for (i = 0; i < ARRAY_SIZE(frs_limits); i++) |
| 328 | if (target_pll >= frs_limits[i]) |
| 329 | break; |
| 330 | |
| 331 | if (i == ARRAY_SIZE(frs_limits) || i == 0) |
| 332 | return -EINVAL; |
| 333 | |
| 334 | frs = i - 1; |
| 335 | max_pll = frs_limits[i - 1]; |
| 336 | min_pll = frs_limits[i]; |
| 337 | |
| 338 | refclk = clk_get_rate(priv->refclk); |
| 339 | |
| 340 | best_diff = UINT_MAX; |
| 341 | best_pll = 0; |
| 342 | best_prd = 0; |
| 343 | best_fbd = 0; |
| 344 | |
| 345 | for (prd = 1; prd <= 16; ++prd) { |
| 346 | u32 divisor = prd * (1 << frs); |
| 347 | u32 fbd; |
| 348 | |
| 349 | for (fbd = 1; fbd <= 512; ++fbd) { |
| 350 | u32 pll, diff, pll_in; |
| 351 | |
| 352 | pll = (u32)div_u64((u64)refclk * fbd, divisor); |
| 353 | |
| 354 | if (pll >= max_pll || pll < min_pll) |
| 355 | continue; |
| 356 | |
| 357 | pll_in = (u32)div_u64((u64)refclk, prd); |
| 358 | if (pll_in < 4000000) |
| 359 | continue; |
| 360 | |
| 361 | diff = max(pll, target_pll) - min(pll, target_pll); |
| 362 | |
| 363 | if (diff < best_diff) { |
| 364 | best_diff = diff; |
| 365 | best_pll = pll; |
| 366 | best_prd = prd; |
| 367 | best_fbd = fbd; |
| 368 | |
| 369 | if (best_diff == 0) |
| 370 | goto found; |
| 371 | } |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | if (best_diff == UINT_MAX) { |
| 376 | log_debug("%s: could not find suitable PLL setup\n", __func__); |
| 377 | return -EINVAL; |
| 378 | } |
| 379 | |
| 380 | found: |
| 381 | priv->fbd = best_fbd; |
| 382 | priv->prd = best_prd; |
| 383 | priv->frs = frs; |
| 384 | priv->dsiclk = best_pll / 2; |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static void tc358768_setup_pll(struct udevice *dev) |
| 390 | { |
| 391 | struct tc358768_priv *priv = dev_get_priv(dev); |
| 392 | u32 fbd, prd, frs; |
| 393 | int ret; |
| 394 | |
| 395 | ret = tc358768_calc_pll(priv, &priv->timing); |
| 396 | if (ret) |
| 397 | log_debug("%s: PLL calculation failed: %d\n", __func__, ret); |
| 398 | |
| 399 | fbd = priv->fbd; |
| 400 | prd = priv->prd; |
| 401 | frs = priv->frs; |
| 402 | |
| 403 | log_debug("%s: PLL: refclk %lu, fbd %u, prd %u, frs %u\n", __func__, |
| 404 | clk_get_rate(priv->refclk), fbd, prd, frs); |
| 405 | log_debug("%s: PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", __func__, |
| 406 | priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); |
| 407 | |
| 408 | /* PRD[15:12] FBD[8:0] */ |
| 409 | tc358768_write(dev, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); |
| 410 | |
| 411 | /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ |
| 412 | tc358768_write(dev, TC358768_PLLCTL1, |
| 413 | (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); |
| 414 | |
| 415 | /* wait for lock */ |
| 416 | mdelay(5); |
| 417 | |
| 418 | /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ |
| 419 | tc358768_write(dev, TC358768_PLLCTL1, |
| 420 | (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); |
| 421 | } |
| 422 | |
| 423 | static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) |
| 424 | { |
| 425 | return DIV_ROUND_UP(ns * 1000, period_ps); |
| 426 | } |
| 427 | |
| 428 | static u32 tc358768_ps_to_ns(u32 ps) |
| 429 | { |
| 430 | return ps / 1000; |
| 431 | } |
| 432 | |
| 433 | static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) |
| 434 | { |
| 435 | return (u32)div_u64((u64)val * NANO, pclk); |
| 436 | } |
| 437 | |
| 438 | /* Convert value in DPI pixel clock units to DSI byte count */ |
| 439 | static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) |
| 440 | { |
| 441 | u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; |
| 442 | u64 n = priv->timing.pixelclock.typ; |
| 443 | |
| 444 | return (u32)div_u64(m + n - 1, n); |
| 445 | } |
| 446 | |
| 447 | static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) |
| 448 | { |
| 449 | u64 m = (u64)val * NANO; |
| 450 | u64 n = priv->dsiclk / 4 * priv->dsi_lanes; |
| 451 | |
| 452 | return (u32)div_u64(m, n); |
| 453 | } |
| 454 | |
| 455 | static int tc358768_attach(struct udevice *dev) |
| 456 | { |
| 457 | struct tc358768_priv *priv = dev_get_priv(dev); |
| 458 | struct mipi_dsi_device *device = &priv->device; |
| 459 | struct display_timing *dt = &priv->timing; |
| 460 | u32 val, val2, lptxcnt, hact, data_type; |
| 461 | s32 raw_val; |
| 462 | u32 hsbyteclk_ps, dsiclk_ps, ui_ps; |
| 463 | u32 dsiclk, hsbyteclk; |
| 464 | int i; |
| 465 | /* In pixelclock units */ |
| 466 | u32 dpi_htot, dpi_data_start; |
| 467 | /* In byte units */ |
| 468 | u32 dsi_dpi_htot, dsi_dpi_data_start; |
| 469 | u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; |
| 470 | const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */ |
| 471 | /* In hsbyteclk units */ |
| 472 | u32 dsi_vsdly; |
| 473 | const u32 internal_dly = 40; |
| 474 | |
| 475 | if (device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { |
| 476 | debug("%s: Non-continuous mode unimplemented, falling back to continuous\n", __func__); |
| 477 | device->mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; |
| 478 | } |
| 479 | |
| 480 | tc358768_hw_enable(priv); |
| 481 | tc358768_sw_reset(dev); |
| 482 | |
| 483 | tc358768_setup_pll(dev); |
| 484 | |
| 485 | dsiclk = priv->dsiclk; |
| 486 | hsbyteclk = dsiclk / 4; |
| 487 | |
| 488 | /* Data Format Control Register */ |
| 489 | val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ |
| 490 | switch (device->format) { |
| 491 | case MIPI_DSI_FMT_RGB888: |
| 492 | val |= (0x3 << 4); |
| 493 | hact = dt->hactive.typ * 3; |
| 494 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; |
| 495 | break; |
| 496 | case MIPI_DSI_FMT_RGB666: |
| 497 | val |= (0x4 << 4); |
| 498 | hact = dt->hactive.typ * 3; |
| 499 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; |
| 500 | break; |
| 501 | case MIPI_DSI_FMT_RGB666_PACKED: |
| 502 | val |= (0x4 << 4) | BIT(3); |
| 503 | hact = dt->hactive.typ * 18 / 8; |
| 504 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; |
| 505 | break; |
| 506 | case MIPI_DSI_FMT_RGB565: |
| 507 | val |= (0x5 << 4); |
| 508 | hact = dt->hactive.typ * 2; |
| 509 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; |
| 510 | break; |
| 511 | default: |
| 512 | log_debug("%s: Invalid data format (%u)\n", |
| 513 | __func__, device->format); |
| 514 | return -EINVAL; |
| 515 | } |
| 516 | |
| 517 | /* |
| 518 | * There are three important things to make TC358768 work correctly, |
| 519 | * which are not trivial to manage: |
| 520 | * |
| 521 | * 1. Keep the DPI line-time and the DSI line-time as close to each |
| 522 | * other as possible. |
| 523 | * 2. TC358768 goes to LP mode after each line's active area. The DSI |
| 524 | * HFP period has to be long enough for entering and exiting LP mode. |
| 525 | * But it is not clear how to calculate this. |
| 526 | * 3. VSDly (video start delay) has to be long enough to ensure that the |
| 527 | * DSI TX does not start transmitting until we have started receiving |
| 528 | * pixel data from the DPI input. It is not clear how to calculate |
| 529 | * this either. |
| 530 | */ |
| 531 | |
| 532 | dpi_htot = dt->hactive.typ + dt->hfront_porch.typ + |
| 533 | dt->hsync_len.typ + dt->hback_porch.typ; |
| 534 | dpi_data_start = dt->hsync_len.typ + dt->hback_porch.typ; |
| 535 | |
| 536 | log_debug("%s: dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", __func__, |
| 537 | dt->hsync_len.typ, dt->hback_porch.typ, dt->hactive.typ, |
| 538 | dt->hfront_porch.typ, dpi_htot); |
| 539 | |
| 540 | log_debug("%s: dpi horiz timing (ns): %u + %u + %u + %u = %u\n", __func__, |
| 541 | tc358768_dpi_to_ns(dt->hsync_len.typ, dt->pixelclock.typ), |
| 542 | tc358768_dpi_to_ns(dt->hback_porch.typ, dt->pixelclock.typ), |
| 543 | tc358768_dpi_to_ns(dt->hactive.typ, dt->pixelclock.typ), |
| 544 | tc358768_dpi_to_ns(dt->hfront_porch.typ, dt->pixelclock.typ), |
| 545 | tc358768_dpi_to_ns(dpi_htot, dt->pixelclock.typ)); |
| 546 | |
| 547 | log_debug("%s: dpi data start (ns): %u + %u = %u\n", __func__, |
| 548 | tc358768_dpi_to_ns(dt->hsync_len.typ, dt->pixelclock.typ), |
| 549 | tc358768_dpi_to_ns(dt->hback_porch.typ, dt->pixelclock.typ), |
| 550 | tc358768_dpi_to_ns(dpi_data_start, dt->pixelclock.typ)); |
| 551 | |
| 552 | dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot); |
| 553 | dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); |
| 554 | |
| 555 | if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { |
| 556 | dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, dt->hsync_len.typ); |
| 557 | dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, dt->hback_porch.typ); |
| 558 | } else { |
| 559 | /* HBP is included in HSW in event mode */ |
| 560 | dsi_hbp = 0; |
| 561 | dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, |
| 562 | dt->hsync_len.typ + |
| 563 | dt->hback_porch.typ); |
| 564 | |
| 565 | /* |
| 566 | * The pixel packet includes the actual pixel data, and: |
| 567 | * DSI packet header = 4 bytes |
| 568 | * DCS code = 1 byte |
| 569 | * DSI packet footer = 2 bytes |
| 570 | */ |
| 571 | dsi_hact = hact + 4 + 1 + 2; |
| 572 | |
| 573 | dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; |
| 574 | |
| 575 | /* |
| 576 | * Here we should check if HFP is long enough for entering LP |
| 577 | * and exiting LP, but it's not clear how to calculate that. |
| 578 | * Instead, this is a naive algorithm that just adjusts the HFP |
| 579 | * and HSW so that HFP is (at least) roughly 2/3 of the total |
| 580 | * blanking time. |
| 581 | */ |
| 582 | if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { |
| 583 | u32 old_hfp = dsi_hfp; |
| 584 | u32 old_hsw = dsi_hsw; |
| 585 | u32 tot = dsi_hfp + dsi_hsw + dsi_hss; |
| 586 | |
| 587 | dsi_hsw = tot / 3; |
| 588 | |
| 589 | /* |
| 590 | * Seems like sometimes HSW has to be divisible by num-lanes, but |
| 591 | * not always... |
| 592 | */ |
| 593 | dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes); |
| 594 | |
| 595 | dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; |
| 596 | |
| 597 | log_debug("%s: hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", |
| 598 | __func__, old_hfp, old_hsw, dsi_hfp, dsi_hsw); |
| 599 | } |
| 600 | |
| 601 | log_debug("%s: dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", __func__, |
| 602 | dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, |
| 603 | dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); |
| 604 | |
| 605 | log_debug("%s: dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", __func__, |
| 606 | tc358768_dsi_bytes_to_ns(priv, dsi_hss), |
| 607 | tc358768_dsi_bytes_to_ns(priv, dsi_hsw), |
| 608 | tc358768_dsi_bytes_to_ns(priv, dsi_hbp), |
| 609 | tc358768_dsi_bytes_to_ns(priv, dsi_hact), |
| 610 | tc358768_dsi_bytes_to_ns(priv, dsi_hfp), |
| 611 | tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + |
| 612 | dsi_hbp + dsi_hact + dsi_hfp)); |
| 613 | } |
| 614 | |
| 615 | /* VSDly calculation */ |
| 616 | |
| 617 | /* Start with the HW internal delay */ |
| 618 | dsi_vsdly = internal_dly; |
| 619 | |
| 620 | /* Convert to byte units as the other variables are in byte units */ |
| 621 | dsi_vsdly *= priv->dsi_lanes; |
| 622 | |
| 623 | /* Do we need more delay, in addition to the internal? */ |
| 624 | if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { |
| 625 | dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; |
| 626 | dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes); |
| 627 | } |
| 628 | |
| 629 | log_debug("%s: dsi data start (bytes) %u + %u + %u + %u = %u\n", __func__, |
| 630 | dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, |
| 631 | dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); |
| 632 | |
| 633 | log_debug("%s: dsi data start (ns) %u + %u + %u + %u = %u\n", __func__, |
| 634 | tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), |
| 635 | tc358768_dsi_bytes_to_ns(priv, dsi_hss), |
| 636 | tc358768_dsi_bytes_to_ns(priv, dsi_hsw), |
| 637 | tc358768_dsi_bytes_to_ns(priv, dsi_hbp), |
| 638 | tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); |
| 639 | |
| 640 | /* Convert back to hsbyteclk */ |
| 641 | dsi_vsdly /= priv->dsi_lanes; |
| 642 | |
| 643 | /* |
| 644 | * The docs say that there is an internal delay of 40 cycles. |
| 645 | * However, we get underflows if we follow that rule. If we |
| 646 | * instead ignore the internal delay, things work. So either |
| 647 | * the docs are wrong or the calculations are wrong. |
| 648 | * |
| 649 | * As a temporary fix, add the internal delay here, to counter |
| 650 | * the subtraction when writing the register. |
| 651 | */ |
| 652 | dsi_vsdly += internal_dly; |
| 653 | |
| 654 | /* Clamp to the register max */ |
| 655 | if (dsi_vsdly - internal_dly > 0x3ff) { |
| 656 | log_warning("%s: VSDly too high, underflows likely\n", __func__); |
| 657 | dsi_vsdly = 0x3ff + internal_dly; |
| 658 | } |
| 659 | |
| 660 | /* VSDly[9:0] */ |
| 661 | tc358768_write(dev, TC358768_VSDLY, dsi_vsdly - internal_dly); |
| 662 | |
| 663 | tc358768_write(dev, TC358768_DATAFMT, val); |
| 664 | tc358768_write(dev, TC358768_DSITX_DT, data_type); |
| 665 | |
| 666 | /* Enable D-PHY (HiZ->LP11) */ |
| 667 | tc358768_write(dev, TC358768_CLW_CNTRL, 0x0000); |
| 668 | /* Enable lanes */ |
| 669 | for (i = 0; i < device->lanes; i++) |
| 670 | tc358768_write(dev, TC358768_D0W_CNTRL + i * 4, 0x0000); |
| 671 | |
| 672 | /* Set up D-PHY CONTTX */ |
| 673 | tc358768_write(dev, TC358768_CLW_DPHYCONTTX, 0x0203); |
| 674 | /* Adjust lanes */ |
| 675 | for (i = 0; i < device->lanes; i++) |
| 676 | tc358768_write(dev, TC358768_D0W_DPHYCONTTX + i * 4, 0x0203); |
| 677 | |
| 678 | /* DSI Timings */ |
| 679 | hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk); |
| 680 | dsiclk_ps = (u32)div_u64(PICO, dsiclk); |
| 681 | ui_ps = dsiclk_ps / 2; |
| 682 | log_debug("%s: dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", |
| 683 | __func__, dsiclk_ps, ui_ps, hsbyteclk_ps); |
| 684 | |
| 685 | /* LP11 > 100us for D-PHY Rx Init */ |
| 686 | val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; |
| 687 | log_debug("%s: LINEINITCNT: 0x%x\n", __func__, val); |
| 688 | tc358768_write(dev, TC358768_LINEINITCNT, val); |
| 689 | |
| 690 | /* LPTimeCnt > 50ns */ |
| 691 | val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; |
| 692 | lptxcnt = val; |
| 693 | log_debug("%s: LPTXTIMECNT: 0x%x\n", __func__, val); |
| 694 | tc358768_write(dev, TC358768_LPTXTIMECNT, val); |
| 695 | |
| 696 | /* 38ns < TCLK_PREPARE < 95ns */ |
| 697 | val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; |
| 698 | log_debug("%s: TCLK_PREPARECNT: 0x%x\n", __func__, val); |
| 699 | /* TCLK_PREPARE + TCLK_ZERO > 300ns */ |
| 700 | val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), |
| 701 | hsbyteclk_ps) - 2; |
| 702 | log_debug("%s: TCLK_ZEROCNT: 0x%x\n", __func__, val2); |
| 703 | val |= val2 << 8; |
| 704 | tc358768_write(dev, TC358768_TCLK_HEADERCNT, val); |
| 705 | |
| 706 | /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ |
| 707 | raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), |
| 708 | hsbyteclk_ps) - 5; |
| 709 | val = clamp(raw_val, 0, 127); |
| 710 | log_debug("%s: TCLK_TRAILCNT: 0x%x\n", __func__, val); |
| 711 | tc358768_write(dev, TC358768_TCLK_TRAILCNT, val); |
| 712 | |
| 713 | /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ |
| 714 | val = 50 + tc358768_ps_to_ns(4 * ui_ps); |
| 715 | val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; |
| 716 | log_debug("%s: THS_PREPARECNT: 0x%x\n", __func__, val); |
| 717 | /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ |
| 718 | raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), |
| 719 | hsbyteclk_ps) - 10; |
| 720 | val2 = clamp(raw_val, 0, 127); |
| 721 | log_debug("%s: THS_ZEROCNT: 0x%x\n", __func__, val2); |
| 722 | val |= val2 << 8; |
| 723 | tc358768_write(dev, TC358768_THS_HEADERCNT, val); |
| 724 | |
| 725 | /* TWAKEUP > 1ms in lptxcnt steps */ |
| 726 | val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps); |
| 727 | val = val / (lptxcnt + 1) - 1; |
| 728 | log_debug("%s: TWAKEUP: 0x%x\n", __func__, val); |
| 729 | tc358768_write(dev, TC358768_TWAKEUP, val); |
| 730 | |
| 731 | /* TCLK_POSTCNT > 60ns + 52*UI */ |
| 732 | val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), |
| 733 | hsbyteclk_ps) - 3; |
| 734 | log_debug("%s: TCLK_POSTCNT: 0x%x\n", __func__, val); |
| 735 | tc358768_write(dev, TC358768_TCLK_POSTCNT, val); |
| 736 | |
| 737 | /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ |
| 738 | raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), |
| 739 | hsbyteclk_ps) - 4; |
| 740 | val = clamp(raw_val, 0, 15); |
| 741 | log_debug("%s: THS_TRAILCNT: 0x%x\n", __func__, val); |
| 742 | tc358768_write(dev, TC358768_THS_TRAILCNT, val); |
| 743 | |
| 744 | val = BIT(0); |
| 745 | for (i = 0; i < device->lanes; i++) |
| 746 | val |= BIT(i + 1); |
| 747 | tc358768_write(dev, TC358768_HSTXVREGEN, val); |
| 748 | |
| 749 | tc358768_write(dev, TC358768_TXOPTIONCNTRL, |
| 750 | (device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); |
| 751 | |
| 752 | /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ |
| 753 | val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); |
| 754 | val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; |
| 755 | log_debug("%s: TXTAGOCNT: 0x%x\n", __func__, val); |
| 756 | val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps), |
| 757 | hsbyteclk_ps) - 2; |
| 758 | log_debug("%s: RXTASURECNT: 0x%x\n", __func__, val2); |
| 759 | val = val << 16 | val2; |
| 760 | tc358768_write(dev, TC358768_BTACNTRL1, val); |
| 761 | |
| 762 | /* START[0] */ |
| 763 | tc358768_write(dev, TC358768_STARTCNTRL, 1); |
| 764 | |
| 765 | if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { |
| 766 | /* Set pulse mode */ |
| 767 | tc358768_write(dev, TC358768_DSI_EVENT, 0); |
| 768 | |
| 769 | /* vact */ |
| 770 | tc358768_write(dev, TC358768_DSI_VACT, dt->vactive.typ); |
| 771 | /* vsw */ |
| 772 | tc358768_write(dev, TC358768_DSI_VSW, dt->vsync_len.typ); |
| 773 | /* vbp */ |
| 774 | tc358768_write(dev, TC358768_DSI_VBPR, dt->vback_porch.typ); |
| 775 | } else { |
| 776 | /* Set event mode */ |
| 777 | tc358768_write(dev, TC358768_DSI_EVENT, 1); |
| 778 | |
| 779 | /* vact */ |
| 780 | tc358768_write(dev, TC358768_DSI_VACT, dt->vactive.typ); |
| 781 | |
| 782 | /* vsw (+ vbp) */ |
| 783 | tc358768_write(dev, TC358768_DSI_VSW, |
| 784 | dt->vsync_len.typ + dt->vback_porch.typ); |
| 785 | /* vbp (not used in event mode) */ |
| 786 | tc358768_write(dev, TC358768_DSI_VBPR, 0); |
| 787 | } |
| 788 | |
| 789 | /* hsw (bytes) */ |
| 790 | tc358768_write(dev, TC358768_DSI_HSW, dsi_hsw); |
| 791 | |
| 792 | /* hbp (bytes) */ |
| 793 | tc358768_write(dev, TC358768_DSI_HBPR, dsi_hbp); |
| 794 | |
| 795 | /* hact (bytes) */ |
| 796 | tc358768_write(dev, TC358768_DSI_HACT, hact); |
| 797 | |
| 798 | /* VSYNC polarity */ |
| 799 | tc358768_update_bits(dev, TC358768_CONFCTL, BIT(5), |
| 800 | (dt->flags & DISPLAY_FLAGS_VSYNC_HIGH) ? BIT(5) : 0); |
| 801 | |
| 802 | /* HSYNC polarity */ |
| 803 | tc358768_update_bits(dev, TC358768_PP_MISC, BIT(0), |
| 804 | (dt->flags & DISPLAY_FLAGS_HSYNC_LOW) ? BIT(0) : 0); |
| 805 | |
| 806 | /* Start DSI Tx */ |
| 807 | tc358768_write(dev, TC358768_DSI_START, 0x1); |
| 808 | |
| 809 | /* Configure DSI_Control register */ |
| 810 | val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; |
| 811 | val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | |
| 812 | 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; |
| 813 | tc358768_write(dev, TC358768_DSI_CONFW, val); |
| 814 | |
| 815 | val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; |
| 816 | val |= (device->lanes - 1) << 1; |
| 817 | |
| 818 | val |= TC358768_DSI_CONTROL_TXMD; |
| 819 | |
| 820 | if (!(device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) |
| 821 | val |= TC358768_DSI_CONTROL_HSCKMD; |
| 822 | |
| 823 | /* |
| 824 | * TODO: Actually MIPI_DSI_MODE_NO_EOT_PACKET |
| 825 | * |
| 826 | * Many of the DSI flags have names opposite to their |
| 827 | * actual effects, e.g. MIPI_DSI_MODE_EOT_PACKET means |
| 828 | * that EoT packets will actually be disabled. |
| 829 | */ |
| 830 | if (device->mode_flags & MIPI_DSI_MODE_EOT_PACKET) |
| 831 | val |= TC358768_DSI_CONTROL_EOTDIS; |
| 832 | |
| 833 | tc358768_write(dev, TC358768_DSI_CONFW, val); |
| 834 | |
| 835 | val = TC358768_DSI_CONFW_MODE_CLR | |
| 836 | TC358768_DSI_CONFW_ADDR_DSI_CONTROL | |
| 837 | TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ |
| 838 | tc358768_write(dev, TC358768_DSI_CONFW, val); |
| 839 | |
| 840 | /* clear FrmStop and RstPtr */ |
| 841 | tc358768_update_bits(dev, TC358768_PP_MISC, 0x3 << 14, 0); |
| 842 | |
| 843 | /* set PP_en */ |
| 844 | tc358768_update_bits(dev, TC358768_CONFCTL, BIT(6), BIT(6)); |
| 845 | |
| 846 | /* Set up panel configuration */ |
| 847 | return panel_enable_backlight(priv->panel); |
| 848 | } |
| 849 | |
| 850 | static int tc358768_set_backlight(struct udevice *dev, int percent) |
| 851 | { |
| 852 | struct tc358768_priv *priv = dev_get_priv(dev); |
| 853 | |
| 854 | return panel_set_backlight(priv->panel, percent); |
| 855 | } |
| 856 | |
| 857 | static int tc358768_panel_timings(struct udevice *dev, |
| 858 | struct display_timing *timing) |
| 859 | { |
| 860 | struct tc358768_priv *priv = dev_get_priv(dev); |
| 861 | |
| 862 | /* Default to positive sync */ |
| 863 | |
| 864 | if (!(priv->timing.flags & |
| 865 | (DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_HSYNC_HIGH))) |
| 866 | priv->timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH; |
| 867 | |
| 868 | if (!(priv->timing.flags & |
| 869 | (DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH))) |
| 870 | priv->timing.flags |= DISPLAY_FLAGS_VSYNC_HIGH; |
| 871 | |
| 872 | memcpy(timing, &priv->timing, sizeof(*timing)); |
| 873 | |
| 874 | return 0; |
| 875 | } |
| 876 | |
| 877 | static int tc358768_setup(struct udevice *dev) |
| 878 | { |
| 879 | struct tc358768_priv *priv = dev_get_priv(dev); |
| 880 | struct mipi_dsi_device *device = &priv->device; |
| 881 | struct mipi_dsi_panel_plat *mipi_plat; |
| 882 | int ret; |
| 883 | |
| 884 | /* The bridge uses 16 bit registers */ |
| 885 | ret = i2c_set_chip_offset_len(dev, 2); |
| 886 | if (ret) { |
| 887 | log_debug("%s: set_chip_offset_len failed: %d\n", |
| 888 | __func__, ret); |
| 889 | return ret; |
| 890 | } |
| 891 | |
| 892 | ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, |
| 893 | "panel", &priv->panel); |
| 894 | if (ret) { |
| 895 | log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret); |
| 896 | return log_ret(ret); |
| 897 | } |
| 898 | |
| 899 | panel_get_display_timing(priv->panel, &priv->timing); |
| 900 | |
| 901 | mipi_plat = dev_get_plat(priv->panel); |
| 902 | mipi_plat->device = device; |
| 903 | |
| 904 | priv->host.dev = (struct device *)dev; |
| 905 | priv->host.ops = &tc358768_dsi_host_ops; |
| 906 | |
| 907 | device->host = &priv->host; |
| 908 | device->lanes = mipi_plat->lanes; |
| 909 | device->format = mipi_plat->format; |
| 910 | device->mode_flags = mipi_plat->mode_flags; |
| 911 | |
| 912 | priv->pd_lines = mipi_dsi_pixel_format_to_bpp(device->format); |
| 913 | priv->dsi_lanes = device->lanes; |
| 914 | |
| 915 | /* get regulators */ |
| 916 | ret = device_get_supply_regulator(dev, "vddc-supply", &priv->vddc); |
| 917 | if (ret) { |
| 918 | log_debug("%s: vddc regulator error: %d\n", __func__, ret); |
| 919 | if (ret != -ENOENT) |
| 920 | return log_ret(ret); |
| 921 | } |
| 922 | |
| 923 | ret = device_get_supply_regulator(dev, "vddmipi-supply", &priv->vddmipi); |
| 924 | if (ret) { |
| 925 | log_debug("%s: vddmipi regulator error: %d\n", __func__, ret); |
| 926 | if (ret != -ENOENT) |
| 927 | return log_ret(ret); |
| 928 | } |
| 929 | |
| 930 | ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio); |
| 931 | if (ret) { |
| 932 | log_debug("%s: vddio regulator error: %d\n", __func__, ret); |
| 933 | if (ret != -ENOENT) |
| 934 | return log_ret(ret); |
| 935 | } |
| 936 | |
| 937 | /* get clk */ |
| 938 | priv->refclk = devm_clk_get(dev, "refclk"); |
| 939 | if (IS_ERR(priv->refclk)) { |
| 940 | log_debug("%s: Could not get refclk: %ld\n", |
| 941 | __func__, PTR_ERR(priv->refclk)); |
| 942 | return PTR_ERR(priv->refclk); |
| 943 | } |
| 944 | |
| 945 | /* get gpios */ |
| 946 | ret = gpio_request_by_name(dev, "reset-gpios", 0, |
| 947 | &priv->reset_gpio, GPIOD_IS_OUT); |
| 948 | if (ret) { |
| 949 | log_debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret); |
| 950 | return ret; |
| 951 | } |
| 952 | |
| 953 | dm_gpio_set_value(&priv->reset_gpio, 1); |
| 954 | |
| 955 | return 0; |
| 956 | } |
| 957 | |
| 958 | static int tc358768_probe(struct udevice *dev) |
| 959 | { |
| 960 | if (device_get_uclass_id(dev->parent) != UCLASS_I2C) |
| 961 | return -EPROTONOSUPPORT; |
| 962 | |
| 963 | return tc358768_setup(dev); |
| 964 | } |
| 965 | |
| 966 | struct panel_ops tc358768_ops = { |
| 967 | .enable_backlight = tc358768_attach, |
| 968 | .set_backlight = tc358768_set_backlight, |
| 969 | .get_display_timing = tc358768_panel_timings, |
| 970 | }; |
| 971 | |
| 972 | static const struct udevice_id tc358768_ids[] = { |
| 973 | { .compatible = "toshiba,tc358768" }, |
| 974 | { .compatible = "toshiba,tc358778" }, |
| 975 | { } |
| 976 | }; |
| 977 | |
| 978 | U_BOOT_DRIVER(tc358768) = { |
| 979 | .name = "tc358768", |
| 980 | .id = UCLASS_PANEL, |
| 981 | .of_match = tc358768_ids, |
| 982 | .ops = &tc358768_ops, |
| 983 | .probe = tc358768_probe, |
| 984 | .priv_auto = sizeof(struct tc358768_priv), |
| 985 | }; |