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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Thomas Chou221d2ac2015-10-22 22:28:53 +08002/*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
7 * Scott McNutt <smcnutt@psyent.com>
Thomas Chou221d2ac2015-10-22 22:28:53 +08008 */
9
Thomas Chou221d2ac2015-10-22 22:28:53 +080010#include <dm.h>
11#include <errno.h>
12#include <timer.h>
13#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Thomas Chou221d2ac2015-10-22 22:28:53 +080015
Thomas Chou90b1d792015-10-31 20:54:16 +080016/* control register */
17#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
18#define ALTERA_TIMER_START BIT(2) /* Start timer */
19#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
20
Thomas Chou221d2ac2015-10-22 22:28:53 +080021struct altera_timer_regs {
22 u32 status; /* Timer status reg */
23 u32 control; /* Timer control reg */
24 u32 periodl; /* Timeout period low */
25 u32 periodh; /* Timeout period high */
26 u32 snapl; /* Snapshot low */
27 u32 snaph; /* Snapshot high */
28};
29
Simon Glassb75b15b2020-12-03 16:55:23 -070030struct altera_timer_plat {
Thomas Chou221d2ac2015-10-22 22:28:53 +080031 struct altera_timer_regs *regs;
Thomas Chou221d2ac2015-10-22 22:28:53 +080032};
33
Sean Anderson947fc2d2020-10-07 14:37:44 -040034static u64 altera_timer_get_count(struct udevice *dev)
Thomas Chou221d2ac2015-10-22 22:28:53 +080035{
Simon Glass95588622020-12-22 19:30:28 -070036 struct altera_timer_plat *plat = dev_get_plat(dev);
Thomas Chou221d2ac2015-10-22 22:28:53 +080037 struct altera_timer_regs *const regs = plat->regs;
38 u32 val;
39
40 /* Trigger update */
41 writel(0x0, &regs->snapl);
42
43 /* Read timer value */
44 val = readl(&regs->snapl) & 0xffff;
45 val |= (readl(&regs->snaph) & 0xffff) << 16;
Sean Anderson947fc2d2020-10-07 14:37:44 -040046 return timer_conv_64(~val);
Thomas Chou221d2ac2015-10-22 22:28:53 +080047}
48
49static int altera_timer_probe(struct udevice *dev)
50{
Simon Glass95588622020-12-22 19:30:28 -070051 struct altera_timer_plat *plat = dev_get_plat(dev);
Thomas Chou221d2ac2015-10-22 22:28:53 +080052 struct altera_timer_regs *const regs = plat->regs;
53
Thomas Chou221d2ac2015-10-22 22:28:53 +080054 writel(0, &regs->status);
55 writel(0, &regs->control);
56 writel(ALTERA_TIMER_STOP, &regs->control);
57
58 writel(0xffff, &regs->periodl);
59 writel(0xffff, &regs->periodh);
60 writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);
61
62 return 0;
63}
64
Simon Glassaad29ae2020-12-03 16:55:21 -070065static int altera_timer_of_to_plat(struct udevice *dev)
Thomas Chou221d2ac2015-10-22 22:28:53 +080066{
Simon Glassb75b15b2020-12-03 16:55:23 -070067 struct altera_timer_plat *plat = dev_get_plat(dev);
Thomas Chou221d2ac2015-10-22 22:28:53 +080068
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +090069 plat->regs = map_physmem(dev_read_addr(dev),
Thomas Choud82a4d32015-11-14 11:15:31 +080070 sizeof(struct altera_timer_regs),
71 MAP_NOCACHE);
Thomas Chou221d2ac2015-10-22 22:28:53 +080072
73 return 0;
74}
75
76static const struct timer_ops altera_timer_ops = {
77 .get_count = altera_timer_get_count,
78};
79
80static const struct udevice_id altera_timer_ids[] = {
Thomas Chou90b1d792015-10-31 20:54:16 +080081 { .compatible = "altr,timer-1.0" },
82 {}
Thomas Chou221d2ac2015-10-22 22:28:53 +080083};
84
85U_BOOT_DRIVER(altera_timer) = {
86 .name = "altera_timer",
87 .id = UCLASS_TIMER,
88 .of_match = altera_timer_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -070089 .of_to_plat = altera_timer_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -070090 .plat_auto = sizeof(struct altera_timer_plat),
Thomas Chou221d2ac2015-10-22 22:28:53 +080091 .probe = altera_timer_probe,
92 .ops = &altera_timer_ops,
Thomas Chou221d2ac2015-10-22 22:28:53 +080093};