blob: 071bd09fef69a9cb4a5735f979e4e031bb8713c1 [file] [log] [blame]
Marek Vasut8cc43682023-05-06 16:43:31 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2023 Marek Vasut <marex@denx.de>
4 */
Marek Vasut8cc43682023-05-06 16:43:31 +02005#include <dm.h>
6#include <malloc.h>
7#include <serial.h>
8#include <wait_bit.h>
9
10#define SET_REG 0x4
11#define CLR_REG 0x8
12
13#define AUART_CTRL0 0x00
14#define AUART_CTRL1 0x10
15#define AUART_CTRL2 0x20
16#define AUART_LINECTRL 0x30
17#define AUART_INTR 0x50
18#define AUART_DATA 0x60
19#define AUART_STAT 0x70
20
21#define AUART_CTRL0_SFTRST BIT(31)
22#define AUART_CTRL0_CLKGATE BIT(30)
23
24#define AUART_CTRL2_UARTEN BIT(0)
25
26#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
27#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
28#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
29
30#define AUART_STAT_TXFE BIT(27)
31#define AUART_STAT_TXFF BIT(25)
32#define AUART_STAT_RXFE BIT(24)
33
34#define AUART_CLK 24000000
35
36struct mxs_auart_uart_priv {
37 void __iomem *base;
38};
39
40static int mxs_auart_uart_setbrg(struct udevice *dev, int baudrate)
41{
42 struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
43 u32 div;
44
45 writel(AUART_CTRL0_CLKGATE, priv->base + AUART_CTRL0 + CLR_REG);
46 writel(AUART_CTRL0_SFTRST, priv->base + AUART_CTRL0 + CLR_REG);
47
48 writel(AUART_CTRL2_UARTEN, priv->base + AUART_CTRL2 + SET_REG);
49
50 writel(0, priv->base + AUART_INTR);
51
52 div = DIV_ROUND_CLOSEST(AUART_CLK * 32, baudrate);
53
54 /* Disable FIFO, baudrate, 8N1. */
55 writel(AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F) |
56 AUART_LINECTRL_BAUD_DIVINT(div >> 6) |
57 AUART_LINECTRL_WLEN(8),
58 priv->base + AUART_LINECTRL);
59
60 return 0;
61}
62
63static int mxs_auart_uart_pending(struct udevice *dev, bool input)
64{
65 struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
66 u32 stat = readl(priv->base + AUART_STAT);
67
68 if (input)
69 return !(stat & AUART_STAT_RXFE);
70
71 return !!(stat & AUART_STAT_TXFE);
72}
73
74static int mxs_auart_uart_putc(struct udevice *dev, const char ch)
75{
76 struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
77 u32 stat = readl(priv->base + AUART_STAT);
78
79 if (stat & AUART_STAT_TXFF)
80 return -EAGAIN;
81
82 writel(ch, priv->base + AUART_DATA);
83
84 return 0;
85}
86
87static int mxs_auart_uart_getc(struct udevice *dev)
88{
89 struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
90
91 if (!mxs_auart_uart_pending(dev, true))
92 return -EAGAIN;
93
94 return readl(priv->base + AUART_DATA) & 0xff;
95}
96
97static int mxs_auart_uart_probe(struct udevice *dev)
98{
99 struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
100
101 priv->base = dev_read_addr_ptr(dev);
102 if (!priv->base)
103 return -EINVAL;
104
105 return mxs_auart_uart_setbrg(dev, CONFIG_BAUDRATE);
106}
107
108static const struct dm_serial_ops mxs_auart_uart_ops = {
109 .putc = mxs_auart_uart_putc,
110 .pending = mxs_auart_uart_pending,
111 .getc = mxs_auart_uart_getc,
112 .setbrg = mxs_auart_uart_setbrg,
113};
114
115static const struct udevice_id mxs_auart_uart_ids[] = {
116 { .compatible = "fsl,imx23-auart", },
117 { .compatible = "fsl,imx28-auart", },
118 { /* sentinel */ }
119};
120
121U_BOOT_DRIVER(mxs_auart_serial) = {
122 .name = "mxs-auart",
123 .id = UCLASS_SERIAL,
124 .of_match = mxs_auart_uart_ids,
125 .probe = mxs_auart_uart_probe,
126 .ops = &mxs_auart_uart_ops,
127 .priv_auto = sizeof(struct mxs_auart_uart_priv),
128};