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git01.mediatek.com / filogic / uboot / 219e52c44cd21f75636527fc583d9fe9379792be / . / drivers / mmc / piton_mmc.c
blob: fed1f8416088ba8b1519d222b23c26a8717b2e1b [file] [log] [blame]
Tianrui Wei8cfc7c52021-07-01 12:54:20 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2009 SAMSUNG Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Jaehoon Chung <jh80.chung@samsung.com>
6 * Portions Copyright 2011-2019 NVIDIA Corporation
7 * Portions Copyright 2021 Tianrui Wei
8 * This file is adapted from tegra_mmc.c
9 * Tianrui Wei <tianrui-wei@outlook.com>
10 */
11
12#include <asm/gpio.h>
13#include <asm/io.h>
Tianrui Wei8cfc7c52021-07-01 12:54:20 +0800[diff] [blame]14#include <div64.h>
15#include <dm.h>
16#include <errno.h>
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/types.h>
21#include <linux/sizes.h>
22#include <log.h>
23#include <mmc.h>
24
25
26#define PITON_MMC_DUMMY_F_MAX 20000000
27#define PITON_MMC_DUMMY_F_MIN 10000000
28#define PITON_MMC_DUMMY_CAPACITY SZ_4G << 3
29#define PITON_MMC_DUMMY_B_MAX SZ_4G
30
31struct piton_mmc_plat {
32 struct mmc_config cfg;
33 struct mmc mmc;
34};
35
36struct piton_mmc_priv {
37 void __iomem *base_addr;
38};
39
40static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
41 struct mmc_data *data)
42{
43 if (!data)
44 return 0;
45
46 struct piton_mmc_priv *priv = dev_get_priv(dev);
47 u32 *buff, *start_addr, *write_src;
48 size_t byte_cnt, start_block;
49
50 buff = (u32 *)data->dest;
51 write_src = (u32 *)data->src;
52 start_block = cmd->cmdarg;
53 start_addr = priv->base_addr + start_block;
54
55 /* if there is a read */
56 for (byte_cnt = data->blocks * data->blocksize; byte_cnt;
57 byte_cnt -= sizeof(u32)) {
58 if (data->flags & MMC_DATA_READ) {
59 *buff++ = readl(start_addr++);
60 }
61 else if (data->flags & MMC_DATA_WRITE) {
62 writel(*write_src++,start_addr++);
63 }
64 }
65 return 0;
66}
67
68static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
69{
70 struct piton_mmc_priv *priv = dev_get_priv(dev);
71 struct piton_mmc_plat *plat = dev_get_plat(dev);
72 struct mmc_config *cfg;
73 struct mmc *mmc;
74 struct blk_desc *bdesc;
75
Johan Jonker8d5d8e02023-03-13 01:32:04 +0100[diff] [blame]76 priv->base_addr = dev_read_addr_ptr(dev);
Tianrui Wei8cfc7c52021-07-01 12:54:20 +0800[diff] [blame]77 cfg = &plat->cfg;
78 cfg->name = "PITON MMC";
79 cfg->host_caps = MMC_MODE_8BIT;
80 cfg->f_max = PITON_MMC_DUMMY_F_MAX;
81 cfg->f_min = PITON_MMC_DUMMY_F_MIN;
82 cfg->voltages = MMC_VDD_21_22;
83
84 mmc = &plat->mmc;
85 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
86 mmc->capacity_user = PITON_MMC_DUMMY_CAPACITY;
87 mmc->capacity_user *= mmc->read_bl_len;
88 mmc->capacity_boot = 0;
89 mmc->capacity_rpmb = 0;
90 for (int i = 0; i < 4; i++)
91 mmc->capacity_gp[i] = 0;
92 mmc->capacity = PITON_MMC_DUMMY_CAPACITY;
93 mmc->has_init = 1;
94
95 bdesc = mmc_get_blk_desc(mmc);
96 bdesc->lun = 0;
97 bdesc->hwpart = 0;
98 bdesc->type = 0;
99 bdesc->blksz = mmc->read_bl_len;
100 bdesc->log2blksz = LOG2(bdesc->blksz);
101 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
102
103 return 0;
104}
105
106static int piton_mmc_getcd(struct udevice *dev)
107{
108 return 1;
109}
110
111static const struct dm_mmc_ops piton_mmc_ops = {
112 .send_cmd = piton_mmc_send_cmd,
113 .get_cd = piton_mmc_getcd,
114};
115
116static int piton_mmc_probe(struct udevice *dev)
117{
118 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
119 struct piton_mmc_plat *plat = dev_get_plat(dev);
120 struct mmc_config *cfg = &plat->cfg;
121
122 cfg->name = dev->name;
123 upriv->mmc = &plat->mmc;
124 upriv->mmc->has_init = 1;
125 upriv->mmc->capacity = PITON_MMC_DUMMY_CAPACITY;
126 upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
127 return 0;
128}
129
130static int piton_mmc_bind(struct udevice *dev)
131{
132 struct piton_mmc_plat *plat = dev_get_plat(dev);
133 struct mmc_config *cfg = &plat->cfg;
134
135 cfg->name = dev->name;
136 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
137 cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
138 cfg->f_min = PITON_MMC_DUMMY_F_MIN;
139 cfg->f_max = PITON_MMC_DUMMY_F_MAX;
140 cfg->b_max = MMC_MAX_BLOCK_LEN;
141
142 return mmc_bind(dev, &plat->mmc, cfg);
143}
144
145static const struct udevice_id piton_mmc_ids[] = {
146 {.compatible = "openpiton,piton-mmc"},
147 {/* sentinel */}
148};
149
150U_BOOT_DRIVER(piton_mmc_drv) = {
151 .name = "piton_mmc",
152 .id = UCLASS_MMC,
153 .of_match = piton_mmc_ids,
154 .of_to_plat = piton_mmc_ofdata_to_platdata,
155 .bind = piton_mmc_bind,
156 .probe = piton_mmc_probe,
157 .ops = &piton_mmc_ops,
158 .plat_auto = sizeof(struct piton_mmc_plat),
159 .priv_auto = sizeof(struct piton_mmc_priv),
160};