blob: 5273b9bfed89ffb01bbb53c91bf747eef059048b [file] [log] [blame]
Benjamin Gaignard77611122018-11-27 13:49:52 +01001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
Patrick Delaunayecd1bac2020-11-06 19:01:39 +01006#define LOG_CATEGORY UCLASS_HWSPINLOCK
7
Benjamin Gaignard77611122018-11-27 13:49:52 +01008#include <clk.h>
9#include <dm.h>
10#include <hwspinlock.h>
Simon Glass9bc15642020-02-03 07:36:16 -070011#include <malloc.h>
Benjamin Gaignard77611122018-11-27 13:49:52 +010012#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060013#include <linux/bitops.h>
Benjamin Gaignard77611122018-11-27 13:49:52 +010014
15#define STM32_MUTEX_COREID BIT(8)
16#define STM32_MUTEX_LOCK_BIT BIT(31)
17#define STM32_MUTEX_NUM_LOCKS 32
18
19struct stm32mp1_hws_priv {
20 fdt_addr_t base;
21};
22
23static int stm32mp1_lock(struct udevice *dev, int index)
24{
25 struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
26 u32 status;
27
28 if (index >= STM32_MUTEX_NUM_LOCKS)
29 return -EINVAL;
30
31 status = readl(priv->base + index * sizeof(u32));
32 if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
33 return -EBUSY;
34
35 writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID,
36 priv->base + index * sizeof(u32));
37
38 status = readl(priv->base + index * sizeof(u32));
39 if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
40 return -EINVAL;
41
42 return 0;
43}
44
45static int stm32mp1_unlock(struct udevice *dev, int index)
46{
47 struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
48
49 if (index >= STM32_MUTEX_NUM_LOCKS)
50 return -EINVAL;
51
52 writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32));
53
54 return 0;
55}
56
57static int stm32mp1_hwspinlock_probe(struct udevice *dev)
58{
59 struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
60 struct clk clk;
61 int ret;
62
63 priv->base = dev_read_addr(dev);
64 if (priv->base == FDT_ADDR_T_NONE)
65 return -EINVAL;
66
67 ret = clk_get_by_index(dev, 0, &clk);
68 if (ret)
69 return ret;
70
Sean Andersond318eb32023-12-16 14:38:42 -050071 return clk_enable(&clk);
Benjamin Gaignard77611122018-11-27 13:49:52 +010072}
73
74static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = {
75 .lock = stm32mp1_lock,
76 .unlock = stm32mp1_unlock,
77};
78
79static const struct udevice_id stm32mp1_hwspinlock_ids[] = {
80 { .compatible = "st,stm32-hwspinlock" },
81 {}
82};
83
84U_BOOT_DRIVER(hwspinlock_stm32mp1) = {
85 .name = "hwspinlock_stm32mp1",
86 .id = UCLASS_HWSPINLOCK,
87 .of_match = stm32mp1_hwspinlock_ids,
88 .ops = &stm32mp1_hwspinlock_ops,
89 .probe = stm32mp1_hwspinlock_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -070090 .priv_auto = sizeof(struct stm32mp1_hws_priv),
Benjamin Gaignard77611122018-11-27 13:49:52 +010091};