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git01.mediatek.com / filogic / uboot / d76f29a352f019fac3ea3935271f0df586c38dea / . / configs / socfpga_sr1500_defconfig
blob: 770ebcd17ad2e1c08be3e7f28a76600516992555 [file] [log] [blame]
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SOCFPGA=y
Masahiro Yamada75794f92016-09-19 21:40:26 +0900[diff] [blame]3CONFIG_SYS_MALLOC_F_LEN=0x2000
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]4CONFIG_TARGET_SOCFPGA_SR1500=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]5CONFIG_SPL_STACK_R_ADDR=0x00800000
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]6CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]7CONFIG_FIT=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]8CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]9CONFIG_VERSION_VARIABLE=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]10# CONFIG_DISPLAY_BOARDINFO is not set
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]11CONFIG_SPL=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]12CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]13CONFIG_SPL_STACK_R=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]14CONFIG_HUSH_PARSER=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]15CONFIG_CMD_BOOTZ=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]16# CONFIG_CMD_IMLS is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]17CONFIG_CMD_ASKENV=y
18CONFIG_CMD_GREPENV=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]19CONFIG_CMD_MEMTEST=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]20# CONFIG_CMD_FLASH is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]21CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]22CONFIG_CMD_SF=y
23CONFIG_CMD_SPI=y
24CONFIG_CMD_I2C=y
25CONFIG_CMD_GPIO=y
26CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]27CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]28CONFIG_CMD_PING=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]29CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]30CONFIG_CMD_TIME=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]31CONFIG_CMD_EXT4=y
32CONFIG_CMD_EXT4_WRITE=y
33CONFIG_CMD_FAT=y
34CONFIG_CMD_FS_GENERIC=y
Heiko Schocher09dbb852016-09-21 07:58:19 +0200[diff] [blame]35CONFIG_CMD_UBI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]36CONFIG_SPL_DM=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]37CONFIG_SPL_DM_SEQ_ALIAS=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]38CONFIG_DM_GPIO=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]39CONFIG_DWAPB_GPIO=y
Stefan Roese78077b62016-04-28 09:47:18 +0200[diff] [blame]40CONFIG_SYS_I2C_DW=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]41CONFIG_DM_MMC=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]42CONFIG_SPI_FLASH=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]43CONFIG_SPI_FLASH_BAR=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]44CONFIG_SPI_FLASH_STMICRO=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]45# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]46CONFIG_DM_ETH=y
47CONFIG_ETH_DESIGNWARE=y
48CONFIG_SYS_NS16550=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]49CONFIG_CADENCE_QSPI=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]50CONFIG_USE_TINY_PRINTF=y