| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Configuration settings for the Renesas GRPEACH board |
| 4 | * |
| 5 | * Copyright (C) 2017-2019 Renesas Electronics |
| 6 | */ |
| 7 | |
| 8 | #ifndef __GRPEACH_H |
| 9 | #define __GRPEACH_H |
| 10 | |
| 11 | /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ |
| 12 | #define CONFIG_SYS_CLK_FREQ 66666666 |
| 13 | |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 14 | /* Miscellaneous */ |
| 15 | #define CONFIG_SYS_PBSIZE 256 |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 16 | |
| 17 | /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ |
| 18 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 19 | #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) |
| 20 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 21 | (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 22 | |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 23 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| 24 | |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 25 | /* Network interface */ |
| 26 | #define CONFIG_SH_ETHER_USE_PORT 0 |
| 27 | #define CONFIG_SH_ETHER_PHY_ADDR 0 |
| 28 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII |
| 29 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK |
| 30 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE |
| 31 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 |
| Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 32 | #define CONFIG_BITBANGMII_MULTI |
| 33 | |
| 34 | #endif /* __GRPEACH_H */ |