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git01.mediatek.com / filogic / uboot / 20fd96c2ec4d5f8cc4afe64fe5f479eebaa32a96 / . / board / BuR / brsmarc1 / board.c
blob: 4c7034614825095943a6662d2840d6bb65e4aa11 [file] [log] [blame]
Hannes Schmelzer82088482019-08-01 07:04:46 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * board.c
4 *
5 * Board functions for B&R BRSMARC1 Board
6 *
7 * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
8 * B&R Industrial Automation GmbH - http://www.br-automation.com
9 *
10 */
11#include <common.h>
12#include <errno.h>
13#include <spl.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/hardware.h>
16#include <asm/arch/omap.h>
17#include <asm/arch/ddr_defs.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/arch/mem.h>
21#include <asm/io.h>
22#include <asm/gpio.h>
23#include <asm/emif.h>
24#include <power/tps65217.h>
25#include "../common/bur_common.h"
26#include "../common/br_resetc.h"
27
28/* -------------------------------------------------------------------------*/
29/* -- defines for used GPIO Hardware -- */
30#define PER_RESET (2 * 32 + 0)
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#if defined(CONFIG_SPL_BUILD)
35static const struct ddr_data ddr3_data = {
36 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
37 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
38 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
39 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
40};
41
42static const struct cmd_control ddr3_cmd_ctrl_data = {
43 .cmd0csratio = MT41K256M16HA125E_RATIO,
44 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
45
46 .cmd1csratio = MT41K256M16HA125E_RATIO,
47 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
48
49 .cmd2csratio = MT41K256M16HA125E_RATIO,
50 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
51};
52
53static struct emif_regs ddr3_emif_reg_data = {
54 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
55 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
56 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
57 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
58 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
59 .zq_config = MT41K256M16HA125E_ZQ_CFG,
60 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
61};
62
63static const struct ctrl_ioregs ddr3_ioregs = {
64 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
65 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
66 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
67 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
68 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
69};
70
71#define OSC (V_OSCK / 1000000)
72const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
73
74void am33xx_spl_board_init(void)
75{
76 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
77 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
78
79 int rc;
80 /*
81 * enable additional clocks of modules which are accessed later from
82 * VxWorks OS
83 */
84 u32 *const clk_domains[] = { 0 };
85 u32 *const clk_modules_specific[] = {
86 &cmwkup->wkup_adctscctrl,
87 &cmper->spi1clkctrl,
88 &cmper->dcan0clkctrl,
89 &cmper->dcan1clkctrl,
90 &cmper->timer4clkctrl,
91 &cmper->timer5clkctrl,
92 &cmper->lcdclkctrl,
93 &cmper->lcdcclkstctrl,
94 0
95 };
96 do_enable_clocks(clk_domains, clk_modules_specific, 1);
97
98 /* setup I2C */
99 enable_i2c_pin_mux();
100
101 /* peripheral reset */
102 rc = gpio_request(PER_RESET, "PER_RESET");
103 if (rc != 0)
104 printf("cannot request PER_RESET GPIO!\n");
105
106 rc = gpio_direction_output(PER_RESET, 0);
107 if (rc != 0)
108 printf("cannot set PER_RESET GPIO!\n");
109
110 /* setup pmic */
111 pmicsetup(0, 0);
112}
113
114const struct dpll_params *get_dpll_ddr_params(void)
115{
116 return &dpll_ddr3;
117}
118
119void sdram_init(void)
120{
121 config_ddr(400, &ddr3_ioregs,
122 &ddr3_data,
123 &ddr3_cmd_ctrl_data,
124 &ddr3_emif_reg_data, 0);
125}
126#endif /* CONFIG_SPL_BUILD */
127#if !defined(CONFIG_SPL_BUILD)
128
129/* decision if backlight is switched on or not on powerup */
130int board_backlightstate(void)
131{
132 u8 bklmask, rstcause;
133 int rc = 0;
134
135 rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
136 rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
137
138 if (rc != 0) {
139 printf("%s: read rstctrl failed!\n", __func__);
140 return 1;
141 }
142
143 if ((rstcause & bklmask) != 0)
144 return 0;
145
146 return 1;
147}
148
149/* Basic board specific setup. run quite after relocation */
150int board_init(void)
151{
152 if (power_tps65217_init(0))
153 printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
154
155 return 0;
156}
157
158#if defined(CONFIG_BOARD_LATE_INIT)
159
160int board_late_init(void)
161{
162 br_resetc_bmode();
163
164 return 0;
165}
166
167#endif /* CONFIG_BOARD_LATE_INIT */
168#endif /* !CONFIG_SPL_BUILD */