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git01.mediatek.com / filogic / uboot / 20e7b022edba34d953ad00f557ebbcbef46ed63e / . / arch / arm / dts / imx8mn-venice-gw7902.dts
blob: d026d965580ecfb5ff66ee498838aff6fdf76623 [file] [log] [blame]
Tim Harvey1a50e742022-02-11 10:48:56 -0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mn.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18
19 aliases {
20 usb0 = &usbotg1;
21 };
22
23 chosen {
24 stdout-path = &uart2;
25 };
26
27 memory@40000000 {
28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x80000000>;
30 };
31
32 can20m: can20m {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <20000000>;
36 clock-output-names = "can20m";
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 user-pb {
43 label = "user_pb";
44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 linux,code = <BTN_0>;
46 };
47
48 user-pb1x {
49 label = "user_pb1x";
50 linux,code = <BTN_1>;
51 interrupt-parent = <&gsc>;
52 interrupts = <0>;
53 };
54
55 key-erased {
56 label = "key_erased";
57 linux,code = <BTN_2>;
58 interrupt-parent = <&gsc>;
59 interrupts = <1>;
60 };
61
62 eeprom-wp {
63 label = "eeprom_wp";
64 linux,code = <BTN_3>;
65 interrupt-parent = <&gsc>;
66 interrupts = <2>;
67 };
68
69 tamper {
70 label = "tamper";
71 linux,code = <BTN_4>;
72 interrupt-parent = <&gsc>;
73 interrupts = <5>;
74 };
75
76 switch-hold {
77 label = "switch_hold";
78 linux,code = <BTN_5>;
79 interrupt-parent = <&gsc>;
80 interrupts = <7>;
81 };
82 };
83
84 led-controller {
85 compatible = "gpio-leds";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_leds>;
88
89 led-0 {
90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_GREEN>;
92 label = "panel1";
93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off";
95 };
96
97 led-1 {
98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_GREEN>;
100 label = "panel2";
101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off";
103 };
104
105 led-2 {
106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_GREEN>;
108 label = "panel3";
109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off";
111 };
112
113 led-3 {
114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_GREEN>;
116 label = "panel4";
117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off";
119 };
120
121 led-4 {
122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_GREEN>;
124 label = "panel5";
125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off";
127 };
128 };
129
130 pps {
131 compatible = "pps-gpio";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135 status = "okay";
136 };
137
138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed";
140 regulator-name = "3P3V";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 };
144
145 reg_usb1_vbus: regulator-usb1 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_reg_usb1>;
148 compatible = "regulator-fixed";
149 regulator-name = "usb_usb1_vbus";
150 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
151 enable-active-high;
152 regulator-min-microvolt = <5000000>;
153 regulator-max-microvolt = <5000000>;
154 };
155
156 reg_wifi: regulator-wifi {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_reg_wl>;
159 compatible = "regulator-fixed";
160 regulator-name = "wifi";
161 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
162 enable-active-high;
163 startup-delay-us = <100>;
164 regulator-min-microvolt = <3300000>;
165 regulator-max-microvolt = <3300000>;
166 };
167};
168
169&A53_0 {
170 cpu-supply = <&buck2>;
171};
172
173&A53_1 {
174 cpu-supply = <&buck2>;
175};
176
177&A53_2 {
178 cpu-supply = <&buck2>;
179};
180
181&A53_3 {
182 cpu-supply = <&buck2>;
183};
184
185&ddrc {
186 operating-points-v2 = <&ddrc_opp_table>;
187
188 ddrc_opp_table: opp-table {
189 compatible = "operating-points-v2";
190
191 opp-25M {
192 opp-hz = /bits/ 64 <25000000>;
193 };
194
195 opp-100M {
196 opp-hz = /bits/ 64 <100000000>;
197 };
198
199 opp-750M {
200 opp-hz = /bits/ 64 <750000000>;
201 };
202 };
203};
204
205&ecspi1 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_spi1>;
208 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
209 status = "okay";
210
211 can@0 {
212 compatible = "microchip,mcp2515";
213 reg = <0>;
214 clocks = <&can20m>;
215 oscillator-frequency = <20000000>;
216 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000>;
219 };
220};
221
222/* off-board header */
223&ecspi2 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_spi2>;
226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
227 status = "okay";
228};
229
230&fec1 {
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_fec1>;
233 phy-mode = "rgmii-id";
234 phy-handle = <&ethphy0>;
235 local-mac-address = [00 00 00 00 00 00];
236 status = "okay";
237
238 mdio {
239 #address-cells = <1>;
240 #size-cells = <0>;
241
242 ethphy0: ethernet-phy@0 {
243 compatible = "ethernet-phy-ieee802.3-c22";
244 reg = <0>;
Tim Harvey3c436182022-04-13 09:09:49 -0700[diff] [blame]245 /* TI DP83867 props */
Tim Harvey1a50e742022-02-11 10:48:56 -0800[diff] [blame]246 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
247 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
248 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
249 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
Tim Harvey3c436182022-04-13 09:09:49 -0700[diff] [blame]250 /* GPY111 props */
251 rx-internal-delay-ps = <2000>;
252 tx-internal-delay-ps = <2500>;
Tim Harvey1a50e742022-02-11 10:48:56 -0800[diff] [blame]253 };
254 };
255};
256
257&i2c1 {
258 clock-frequency = <100000>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_i2c1>;
261 status = "okay";
262
263 gsc: gsc@20 {
264 compatible = "gw,gsc";
265 reg = <0x20>;
266 pinctrl-0 = <&pinctrl_gsc>;
267 interrupt-parent = <&gpio2>;
268 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
269 interrupt-controller;
270 #interrupt-cells = <1>;
271
272 adc {
273 compatible = "gw,gsc-adc";
274 #address-cells = <1>;
275 #size-cells = <0>;
276
277 channel@6 {
278 gw,mode = <0>;
279 reg = <0x06>;
280 label = "temp";
281 };
282
283 channel@8 {
284 gw,mode = <1>;
285 reg = <0x08>;
286 label = "vdd_bat";
287 };
288
289 channel@82 {
290 gw,mode = <2>;
291 reg = <0x82>;
292 label = "vin";
293 gw,voltage-divider-ohms = <22100 1000>;
294 gw,voltage-offset-microvolt = <700000>;
295 };
296
297 channel@84 {
298 gw,mode = <2>;
299 reg = <0x84>;
300 label = "vin_4p0";
301 gw,voltage-divider-ohms = <10000 10000>;
302 };
303
304 channel@86 {
305 gw,mode = <2>;
306 reg = <0x86>;
307 label = "vdd_3p3";
308 gw,voltage-divider-ohms = <10000 10000>;
309 };
310
311 channel@88 {
312 gw,mode = <2>;
313 reg = <0x88>;
314 label = "vdd_0p9";
315 };
316
317 channel@8c {
318 gw,mode = <2>;
319 reg = <0x8c>;
320 label = "vdd_soc";
321 };
322
323 channel@8e {
324 gw,mode = <2>;
325 reg = <0x8e>;
326 label = "vdd_arm";
327 };
328
329 channel@90 {
330 gw,mode = <2>;
331 reg = <0x90>;
332 label = "vdd_1p8";
333 };
334
335 channel@92 {
336 gw,mode = <2>;
337 reg = <0x92>;
338 label = "vdd_dram";
339 };
340
341 channel@98 {
342 gw,mode = <2>;
343 reg = <0x98>;
344 label = "vdd_1p0";
345 };
346
347 channel@9a {
348 gw,mode = <2>;
349 reg = <0x9a>;
350 label = "vdd_2p5";
351 gw,voltage-divider-ohms = <10000 10000>;
352 };
353
Tim Harveyf6d4bc42022-03-08 10:44:43 -0800[diff] [blame]354 channel@9c {
355 gw,mode = <2>;
356 reg = <0x9c>;
357 label = "vdd_5p0";
358 gw,voltage-divider-ohms = <10000 10000>;
359 };
360
Tim Harvey1a50e742022-02-11 10:48:56 -0800[diff] [blame]361 channel@a2 {
362 gw,mode = <2>;
363 reg = <0xa2>;
364 label = "vdd_gsc";
365 gw,voltage-divider-ohms = <10000 10000>;
366 };
367 };
368 };
369
370 gpio: gpio@23 {
371 compatible = "nxp,pca9555";
372 reg = <0x23>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 interrupt-parent = <&gsc>;
376 interrupts = <4>;
377 };
378
379 pmic@4b {
380 compatible = "rohm,bd71847";
381 reg = <0x4b>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_pmic>;
384 interrupt-parent = <&gpio3>;
385 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
386 rohm,reset-snvs-powered;
387 #clock-cells = <0>;
388 clocks = <&osc_32k 0>;
389 clock-output-names = "clk-32k-out";
390
391 regulators {
392 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
393 BUCK1 {
394 regulator-name = "buck1";
395 regulator-min-microvolt = <700000>;
396 regulator-max-microvolt = <1300000>;
397 regulator-boot-on;
398 regulator-always-on;
399 regulator-ramp-delay = <1250>;
400 };
401
402 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
403 buck2: BUCK2 {
404 regulator-name = "buck2";
405 regulator-min-microvolt = <700000>;
406 regulator-max-microvolt = <1300000>;
407 regulator-boot-on;
408 regulator-always-on;
409 regulator-ramp-delay = <1250>;
410 rohm,dvs-run-voltage = <1000000>;
411 rohm,dvs-idle-voltage = <900000>;
412 };
413
414 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
415 BUCK3 {
416 regulator-name = "buck3";
417 regulator-min-microvolt = <700000>;
418 regulator-max-microvolt = <1350000>;
419 regulator-boot-on;
420 regulator-always-on;
421 };
422
423 /* vdd_3p3 */
424 BUCK4 {
425 regulator-name = "buck4";
426 regulator-min-microvolt = <3000000>;
427 regulator-max-microvolt = <3300000>;
428 regulator-boot-on;
429 regulator-always-on;
430 };
431
432 /* vdd_1p8 */
433 BUCK5 {
434 regulator-name = "buck5";
435 regulator-min-microvolt = <1605000>;
436 regulator-max-microvolt = <1995000>;
437 regulator-boot-on;
438 regulator-always-on;
439 };
440
441 /* vdd_dram */
442 BUCK6 {
443 regulator-name = "buck6";
444 regulator-min-microvolt = <800000>;
445 regulator-max-microvolt = <1400000>;
446 regulator-boot-on;
447 regulator-always-on;
448 };
449
450 /* nvcc_snvs_1p8 */
451 LDO1 {
452 regulator-name = "ldo1";
453 regulator-min-microvolt = <1600000>;
454 regulator-max-microvolt = <1900000>;
455 regulator-boot-on;
456 regulator-always-on;
457 };
458
459 /* vdd_snvs_0p8 */
460 LDO2 {
461 regulator-name = "ldo2";
462 regulator-min-microvolt = <800000>;
463 regulator-max-microvolt = <900000>;
464 regulator-boot-on;
465 regulator-always-on;
466 };
467
468 /* vdda_1p8 */
469 LDO3 {
470 regulator-name = "ldo3";
471 regulator-min-microvolt = <1800000>;
472 regulator-max-microvolt = <3300000>;
473 regulator-boot-on;
474 regulator-always-on;
475 };
476
477 LDO4 {
478 regulator-name = "ldo4";
479 regulator-min-microvolt = <900000>;
480 regulator-max-microvolt = <1800000>;
481 regulator-boot-on;
482 regulator-always-on;
483 };
484
485 LDO6 {
486 regulator-name = "ldo6";
487 regulator-min-microvolt = <900000>;
488 regulator-max-microvolt = <1800000>;
489 regulator-boot-on;
490 regulator-always-on;
491 };
492 };
493 };
494
495 eeprom@50 {
496 compatible = "atmel,24c02";
497 reg = <0x50>;
498 pagesize = <16>;
499 };
500
501 eeprom@51 {
502 compatible = "atmel,24c02";
503 reg = <0x51>;
504 pagesize = <16>;
505 };
506
507 eeprom@52 {
508 compatible = "atmel,24c02";
509 reg = <0x52>;
510 pagesize = <16>;
511 };
512
513 eeprom@53 {
514 compatible = "atmel,24c02";
515 reg = <0x53>;
516 pagesize = <16>;
517 };
518
519 rtc@68 {
520 compatible = "dallas,ds1672";
521 reg = <0x68>;
522 };
523};
524
525&i2c2 {
526 clock-frequency = <400000>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_i2c2>;
529 status = "okay";
530
531 accelerometer@19 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_accel>;
534 compatible = "st,lis2de12";
535 reg = <0x19>;
536 st,drdy-int-pin = <1>;
537 interrupt-parent = <&gpio1>;
538 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
539 interrupt-names = "INT1";
540 };
541
542 secure-element@60 {
543 compatible = "nxp,se050";
544 reg = <0x60>;
545 };
546};
547
548/* off-board header */
549&i2c3 {
550 clock-frequency = <400000>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_i2c3>;
553 status = "okay";
554};
555
556/* off-board header */
557&i2c4 {
558 clock-frequency = <400000>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_i2c4>;
561 status = "okay";
562};
563
564/* off-board header */
565&sai3 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_sai3>;
568 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
569 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
570 assigned-clock-rates = <24576000>;
571 status = "okay";
572};
573
574/* RS232/RS485/RS422 selectable */
575&uart1 {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
578 status = "okay";
579};
580
581/* RS232 console */
582&uart2 {
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_uart2>;
585 status = "okay";
586};
587
588/* bluetooth HCI */
589&uart3 {
590 pinctrl-names = "default";
591 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
592 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
593 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
594 status = "okay";
595
596 bluetooth {
597 compatible = "brcm,bcm4330-bt";
598 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
599 };
600};
601
602/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
603&uart4 {
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_uart4>;
606 status = "okay";
607};
608
609&usbotg1 {
610 dr_mode = "host";
611 vbus-supply = <&reg_usb1_vbus>;
612 disable-over-current;
613 status = "okay";
614};
615
616/* SDIO WiFi */
617&usdhc2 {
618 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_usdhc2>;
620 bus-width = <4>;
621 non-removable;
622 vmmc-supply = <&reg_wifi>;
623 status = "okay";
624};
625
626/* eMMC */
627&usdhc3 {
628 pinctrl-names = "default", "state_100mhz", "state_200mhz";
629 pinctrl-0 = <&pinctrl_usdhc3>;
630 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
631 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
632 bus-width = <8>;
633 non-removable;
634 status = "okay";
635};
636
637&wdog1 {
638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_wdog>;
640 fsl,ext-reset-output;
641 status = "okay";
642};
643
644&iomuxc {
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_hog>;
647
648 pinctrl_hog: hoggrp {
649 fsl,pins = <
650 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
651 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
652 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
653 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
654 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
655 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
656 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
657 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
658 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
659 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
660 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
661 >;
662 };
663
664 pinctrl_accel: accelgrp {
665 fsl,pins = <
666 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
667 >;
668 };
669
670 pinctrl_fec1: fec1grp {
671 fsl,pins = <
672 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
673 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
674 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
675 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
676 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
677 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
678 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
679 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
680 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
681 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
682 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
683 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
684 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
685 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
686 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
687 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
688 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
689 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
690 >;
691 };
692
693 pinctrl_gsc: gscgrp {
694 fsl,pins = <
695 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
696 >;
697 };
698
699 pinctrl_i2c1: i2c1grp {
700 fsl,pins = <
701 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
702 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
703 >;
704 };
705
706 pinctrl_i2c2: i2c2grp {
707 fsl,pins = <
708 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
709 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
710 >;
711 };
712
713 pinctrl_i2c3: i2c3grp {
714 fsl,pins = <
715 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
716 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
717 >;
718 };
719
720 pinctrl_i2c4: i2c4grp {
721 fsl,pins = <
722 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
723 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
724 >;
725 };
726
727 pinctrl_gpio_leds: gpioledgrp {
728 fsl,pins = <
729 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
730 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
731 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
732 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
733 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
734 >;
735 };
736
737 pinctrl_pmic: pmicgrp {
738 fsl,pins = <
739 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
740 >;
741 };
742
743 pinctrl_pps: ppsgrp {
744 fsl,pins = <
745 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
746 >;
747 };
748
749 pinctrl_reg_wl: regwlgrp {
750 fsl,pins = <
751 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
752 >;
753 };
754
755 pinctrl_reg_usb1: regusb1grp {
756 fsl,pins = <
757 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
758 >;
759 };
760
761 pinctrl_sai3: sai3grp {
762 fsl,pins = <
763 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
764 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
765 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
766 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
767 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
768 >;
769 };
770
771 pinctrl_spi1: spi1grp {
772 fsl,pins = <
773 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
774 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
775 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
776 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
777 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
778 >;
779 };
780
781 pinctrl_spi2: spi2grp {
782 fsl,pins = <
783 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
784 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
785 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
786 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
787 >;
788 };
789
790 pinctrl_uart1: uart1grp {
791 fsl,pins = <
792 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
793 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
794 >;
795 };
796
797 pinctrl_uart1_gpio: uart1gpiogrp {
798 fsl,pins = <
799 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
800 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
801 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
802 >;
803 };
804
805 pinctrl_uart2: uart2grp {
806 fsl,pins = <
807 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
808 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
809 >;
810 };
811
812 pinctrl_uart3_gpio: uart3_gpiogrp {
813 fsl,pins = <
814 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
815 >;
816 };
817
818 pinctrl_uart3: uart3grp {
819 fsl,pins = <
820 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
821 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
822 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
823 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
824 >;
825 };
826
827 pinctrl_uart4: uart4grp {
828 fsl,pins = <
829 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
830 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
831 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
832 >;
833 };
834
835 pinctrl_usdhc2: usdhc2grp {
836 fsl,pins = <
837 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
838 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
839 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
840 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
841 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
842 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
843 >;
844 };
845
846 pinctrl_usdhc3: usdhc3grp {
847 fsl,pins = <
848 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
849 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
850 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
851 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
852 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
853 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
854 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
855 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
856 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
857 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
858 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
859 >;
860 };
861
862 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
863 fsl,pins = <
864 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
865 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
866 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
867 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
868 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
869 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
870 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
871 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
872 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
873 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
874 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
875 >;
876 };
877
878 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
879 fsl,pins = <
880 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
881 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
882 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
883 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
884 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
885 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
886 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
887 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
888 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
889 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
890 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
891 >;
892 };
893
894 pinctrl_wdog: wdoggrp {
895 fsl,pins = <
896 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
897 >;
898 };
899};