Hans de Goede | b728aae | 2015-01-21 16:14:00 +0100 | [diff] [blame] | 1 | /* DRAM parameters for auto dram configuration on sun5i and sun7i */ |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 2 | |
| 3 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 4 | #include <init.h> |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 5 | #include <asm/arch/dram.h> |
| 6 | |
| 7 | static struct dram_para dram_para = { |
| 8 | .clock = CONFIG_DRAM_CLK, |
Siarhei Siamashka | 47359bb | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 9 | .mbus_clock = CONFIG_DRAM_MBUS_CLK, |
Giulio Benetti | 0fe7a5f | 2021-12-03 00:57:54 +0100 | [diff] [blame] | 10 | .type = DRAM_MEMORY_TYPE_DDR3, |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 11 | .rank_num = 1, |
| 12 | .density = 0, |
| 13 | .io_width = 0, |
| 14 | .bus_width = 0, |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 15 | .zq = CONFIG_DRAM_ZQ, |
Hans de Goede | ffdc05c | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 16 | .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN), |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 17 | .size = 0, |
Siarhei Siamashka | 9900db1 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 18 | #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC |
| 19 | .cas = 9, |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 20 | .tpr0 = 0x42d899b7, |
| 21 | .tpr1 = 0xa090, |
| 22 | .tpr2 = 0x22a00, |
Siarhei Siamashka | 9900db1 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 23 | .emr2 = 0x10, |
| 24 | #else |
| 25 | # include "dram_timings_sun4i.h" |
Siarhei Siamashka | 47359bb | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 26 | .active_windowing = 1, |
Siarhei Siamashka | 9900db1 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 27 | #endif |
Adam Sampson | e954e92 | 2015-02-23 20:44:10 +0000 | [diff] [blame] | 28 | .tpr3 = CONFIG_DRAM_TPR3, |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 29 | .tpr4 = 0, |
| 30 | .tpr5 = 0, |
| 31 | .emr1 = CONFIG_DRAM_EMR1, |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 32 | .emr3 = 0, |
Siarhei Siamashka | 47359bb | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 33 | .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, |
Hans de Goede | 7ee8cd1 | 2015-01-17 22:31:30 +0100 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | unsigned long sunxi_dram_init(void) |
| 37 | { |
| 38 | return dramc_init(&dram_para); |
| 39 | } |