Ibai Erkiaga | c8a3efa | 2019-09-27 11:37:01 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Xilinx Zynq MPSoC Firmware driver |
| 4 | * |
| 5 | * Copyright (C) 2018-2019 Xilinx, Inc. |
| 6 | */ |
| 7 | |
| 8 | #ifndef _ZYNQMP_FIRMWARE_H_ |
| 9 | #define _ZYNQMP_FIRMWARE_H_ |
| 10 | |
| 11 | enum pm_api_id { |
| 12 | PM_GET_API_VERSION = 1, |
| 13 | PM_SET_CONFIGURATION, |
Michal Simek | e50c104 | 2019-10-04 15:25:18 +0200 | [diff] [blame] | 14 | PM_GET_NODE_STATUS, |
| 15 | PM_GET_OPERATING_CHARACTERISTIC, |
| 16 | PM_REGISTER_NOTIFIER, |
| 17 | PM_REQUEST_SUSPEND, |
| 18 | PM_SELF_SUSPEND, |
| 19 | PM_FORCE_POWERDOWN, |
| 20 | PM_ABORT_SUSPEND, |
| 21 | PM_REQUEST_WAKEUP, |
| 22 | PM_SET_WAKEUP_SOURCE, |
| 23 | PM_SYSTEM_SHUTDOWN, |
| 24 | PM_REQUEST_NODE, |
| 25 | PM_RELEASE_NODE, |
| 26 | PM_SET_REQUIREMENT, |
| 27 | PM_SET_MAX_LATENCY, |
| 28 | PM_RESET_ASSERT, |
| 29 | PM_RESET_GET_STATUS, |
| 30 | PM_MMIO_WRITE, |
| 31 | PM_MMIO_READ, |
| 32 | PM_PM_INIT_FINALIZE, |
| 33 | PM_FPGA_LOAD, |
| 34 | PM_FPGA_GET_STATUS, |
| 35 | PM_GET_CHIPID, |
| 36 | PM_SECURE_SHA = 26, |
| 37 | PM_SECURE_RSA, |
| 38 | PM_PINCTRL_REQUEST, |
| 39 | PM_PINCTRL_RELEASE, |
| 40 | PM_PINCTRL_GET_FUNCTION, |
| 41 | PM_PINCTRL_SET_FUNCTION, |
| 42 | PM_PINCTRL_CONFIG_PARAM_GET, |
| 43 | PM_PINCTRL_CONFIG_PARAM_SET, |
| 44 | PM_IOCTL, |
| 45 | PM_QUERY_DATA, |
| 46 | PM_CLOCK_ENABLE, |
| 47 | PM_CLOCK_DISABLE, |
| 48 | PM_CLOCK_GETSTATE, |
| 49 | PM_CLOCK_SETDIVIDER, |
| 50 | PM_CLOCK_GETDIVIDER, |
| 51 | PM_CLOCK_SETRATE, |
| 52 | PM_CLOCK_GETRATE, |
| 53 | PM_CLOCK_SETPARENT, |
| 54 | PM_CLOCK_GETPARENT, |
| 55 | PM_SECURE_IMAGE, |
| 56 | PM_FPGA_READ = 46, |
| 57 | PM_SECURE_AES, |
| 58 | PM_CLOCK_PLL_GETPARAM = 49, |
| 59 | PM_REGISTER_ACCESS = 52, |
| 60 | PM_EFUSE_ACCESS, |
| 61 | PM_FEATURE_CHECK = 63, |
| 62 | PM_API_MAX, |
Ibai Erkiaga | c8a3efa | 2019-09-27 11:37:01 +0100 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | #define PM_SIP_SVC 0xc2000000 |
Ibai Erkiaga | c8a3efa | 2019-09-27 11:37:01 +0100 | [diff] [blame] | 66 | |
| 67 | #define ZYNQMP_PM_VERSION_MAJOR 1 |
| 68 | #define ZYNQMP_PM_VERSION_MINOR 0 |
| 69 | #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 |
| 70 | #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF |
| 71 | |
| 72 | #define ZYNQMP_PM_VERSION \ |
| 73 | ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ |
| 74 | ZYNQMP_PM_VERSION_MINOR) |
| 75 | |
| 76 | #define ZYNQMP_PM_VERSION_INVALID ~0 |
| 77 | |
| 78 | #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) |
| 79 | |
| 80 | unsigned int zynqmp_firmware_version(void); |
Michal Simek | a95f0d9 | 2019-09-27 14:20:00 +0200 | [diff] [blame] | 81 | void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); |
Michal Simek | 142fb5b | 2019-10-04 15:52:43 +0200 | [diff] [blame] | 82 | int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, |
Michal Simek | 81efd2a | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 83 | u32 arg3, u32 *ret_payload); |
Ibai Erkiaga | c8a3efa | 2019-09-27 11:37:01 +0100 | [diff] [blame] | 84 | |
| 85 | #endif /* _ZYNQMP_FIRMWARE_H_ */ |