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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Phil Sutterd76eba62015-12-25 14:41:25 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Phil Sutterd76eba62015-12-25 14:41:25 +01004 */
5
6#ifndef _CONFIG_SYNOLOGY_DS414_H
7#define _CONFIG_SYNOLOGY_DS414_H
8
Phil Sutteref534b22021-03-07 22:22:27 +01009/* Vendor kernel expects this MACH_TYPE */
10#define CONFIG_MACH_TYPE 3036
11
Phil Sutterd76eba62015-12-25 14:41:25 +010012/*
13 * High Level Configuration Options (easy to change)
14 */
Phil Sutterd76eba62015-12-25 14:41:25 +010015
16/*
17 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
18 * for DDR ECC byte filling in the SPL before loading the main
19 * U-Boot into it.
20 */
Phil Sutterd76eba62015-12-25 14:41:25 +010021
Phil Sutterd76eba62015-12-25 14:41:25 +010022/* I2C */
Simon Glass0529b592021-07-10 21:14:32 -060023#define CONFIG_SYS_I2C_LEGACY
Phil Sutterd76eba62015-12-25 14:41:25 +010024#define CONFIG_SYS_I2C_MVTWSI
25#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
26#define CONFIG_SYS_I2C_SLAVE 0x0
27#define CONFIG_SYS_I2C_SPEED 100000
28
Phil Sutterd76eba62015-12-25 14:41:25 +010029/* PCIe support */
30#ifndef CONFIG_SPL_BUILD
Phil Sutterd76eba62015-12-25 14:41:25 +010031#define CONFIG_PCI_SCAN_SHOW
32#endif
33
34/* USB/EHCI/XHCI configuration */
Phil Sutterd76eba62015-12-25 14:41:25 +010035#define CONFIG_EHCI_IS_TDI
Phil Sutterd76eba62015-12-25 14:41:25 +010036
37/*
38 * mv-common.h should be defined after CMD configs since it used them
39 * to enable certain macros
40 */
41#include "mv-common.h"
42
43/*
44 * Memory layout while starting into the bin_hdr via the
45 * BootROM:
46 *
47 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
48 * 0x4000.4030 bin_hdr start address
49 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
50 * 0x4007.fffc BootROM stack top
51 *
52 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
53 * L2 cache thus cannot be used.
54 */
55
56/* SPL */
57/* Defines for SPL */
Phil Sutterd76eba62015-12-25 14:41:25 +010058#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
59
60#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
61#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
62
63#ifdef CONFIG_SPL_BUILD
64#define CONFIG_SYS_MALLOC_SIMPLE
65#endif
66
67#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
68#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
69
Phil Sutterd76eba62015-12-25 14:41:25 +010070/* DS414 bus width is 32bits */
71#define CONFIG_DDR_32BIT
72
Phil Sutterd76eba62015-12-25 14:41:25 +010073/* Default Environment */
Phil Sutterd76eba62015-12-25 14:41:25 +010074#define CONFIG_LOADADDR 0x80000
Phil Sutteref534b22021-03-07 22:22:27 +010075#define CONFIG_BOOTCOMMAND \
76 "sf probe; " \
77 "sf read ${loadaddr} 0xd0000 0x2d0000; " \
78 "sf read ${ramdisk_addr_r} 0x3a0000 0x430000; " \
79 "bootm ${loadaddr} ${ramdisk_addr_r}"
80
81#define CONFIG_EXTRA_ENV_SETTINGS \
82 "initrd_high=0xffffffff\0" \
83 "ramdisk_addr_r=0x8000000\0" \
84 "usb0Mode=host\0usb1Mode=host\0usb2Mode=device\0" \
Phil Sutter6d1bcbf2021-03-05 21:05:45 +010085 "ethmtu=1500\0eth1mtu=1500\0" \
86 "update_uboot=sf probe; dhcp; " \
87 "mw.b ${loadaddr} 0x0 0xd0000; " \
88 "tftpboot ${loadaddr} u-boot-spl.kwb; " \
89 "sf update ${loadaddr} 0x0 0xd0000\0"
90
Phil Sutterd76eba62015-12-25 14:41:25 +010091
Phil Sutter246a61f2021-01-03 23:06:44 +010092/* increase autoneg timeout, my NIC sucks */
93#define PHY_ANEG_TIMEOUT 16000
94
Phil Sutterd76eba62015-12-25 14:41:25 +010095#endif /* _CONFIG_SYNOLOGY_DS414_H */