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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewf6afe722007-06-18 13:50:13 -05002/*
3 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewf6afe722007-06-18 13:50:13 -05007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5329EVB_H
14#define _M5329EVB_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChung Liewf6afe722007-06-18 13:50:13 -050020
TsiChungLiewdb0022d2007-08-05 03:19:10 -050021#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020022#define CONFIG_SYS_UART_PORT (0)
TsiChung Liewf6afe722007-06-18 13:50:13 -050023
24#undef CONFIG_WATCHDOG
25#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
26
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020027#define CONFIG_SYS_UNIFY_CACHE
TsiChung Liewf6afe722007-06-18 13:50:13 -050028
TsiChung Liewf6afe722007-06-18 13:50:13 -050029#ifdef CONFIG_MCFFEC
TsiChung Liewb3162452008-03-30 01:22:13 -050030# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031# define CONFIG_SYS_DISCOVER_PHY
32# define CONFIG_SYS_RX_ETH_BUFFER 8
33# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
35# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liewf6afe722007-06-18 13:50:13 -050036# define FECDUPLEX FULL
37# define FECSPEED _100BASET
38# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
40# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liewf6afe722007-06-18 13:50:13 -050041# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020042# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liewf6afe722007-06-18 13:50:13 -050043#endif
44
TsiChung Liewf6afe722007-06-18 13:50:13 -050045#define CONFIG_MCFRTC
TsiChungLiew2e0aeef2007-07-05 22:39:07 -050046#undef RTC_DEBUG
TsiChung Liewf6afe722007-06-18 13:50:13 -050047
48/* Timer */
49#define CONFIG_MCFTMR
TsiChung Liewf6afe722007-06-18 13:50:13 -050050
TsiChungLiew876343b2007-08-05 04:11:20 -050051/* I2C */
Simon Glass0529b592021-07-10 21:14:32 -060052#define CONFIG_SYS_I2C_LEGACY
Heiko Schocherf2850742012-10-24 13:48:22 +020053#define CONFIG_SYS_I2C_FSL
54#define CONFIG_SYS_FSL_I2C_SPEED 80000
55#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
56#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew876343b2007-08-05 04:11:20 -050058
TsiChungLiewaedd3d72007-08-15 15:39:17 -050059#define CONFIG_UDP_CHECKSUM
60
TsiChung Liewf6afe722007-06-18 13:50:13 -050061#ifdef CONFIG_MCFFEC
TsiChungLiew876343b2007-08-05 04:11:20 -050062# define CONFIG_IPADDR 192.162.1.2
63# define CONFIG_NETMASK 255.255.255.0
64# define CONFIG_SERVERIP 192.162.1.1
TsiChung Liewf6afe722007-06-18 13:50:13 -050065# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liewf6afe722007-06-18 13:50:13 -050066#endif /* FEC_ENET */
67
Mario Six790d8442018-03-28 14:38:20 +020068#define CONFIG_HOSTNAME "M5329EVB"
TsiChung Liewf6afe722007-06-18 13:50:13 -050069#define CONFIG_EXTRA_ENV_SETTINGS \
70 "netdev=eth0\0" \
71 "loadaddr=40010000\0" \
72 "u-boot=u-boot.bin\0" \
73 "load=tftp ${loadaddr) ${u-boot}\0" \
74 "upd=run load; run prog\0" \
Jason Jinded4eb42011-08-19 10:10:40 +080075 "prog=prot off 0 3ffff;" \
76 "era 0 3ffff;" \
TsiChung Liewf6afe722007-06-18 13:50:13 -050077 "cp.b ${loadaddr} 0 ${filesize};" \
78 "save\0" \
79 ""
80
TsiChungLiew876343b2007-08-05 04:11:20 -050081#define CONFIG_PRAM 512 /* 512 KB */
TsiChung Liewf6afe722007-06-18 13:50:13 -050082
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChung Liewf6afe722007-06-18 13:50:13 -050084
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_CLK 80000000
86#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChung Liewf6afe722007-06-18 13:50:13 -050087
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liewf6afe722007-06-18 13:50:13 -050089
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewec8468f2007-08-05 04:31:18 -050091
TsiChung Liewf6afe722007-06-18 13:50:13 -050092/*
93 * Low Level Configuration Settings
94 * (address mappings, register initial values, etc.)
95 * You should know what you are doing if you make changes here.
96 */
97/*-----------------------------------------------------------------------
98 * Definitions for initial stack pointer and data area (in DPRAM)
99 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200101#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk0191e472010-10-26 14:34:52 +0200103#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liewf6afe722007-06-18 13:50:13 -0500105
106/*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500110 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_BASE 0x40000000
112#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
113#define CONFIG_SYS_SDRAM_CFG1 0x53722730
114#define CONFIG_SYS_SDRAM_CFG2 0x56670000
115#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
116#define CONFIG_SYS_SDRAM_EMOD 0x40010000
117#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChung Liewf6afe722007-06-18 13:50:13 -0500118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
120#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
123#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500124
125/*
126 * For booting Linux, the board info and command line data
127 * have to be in the first 8 MB of memory, since this is
128 * the maximum mapped by the Linux kernel during initialization ??
129 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew25a00632009-01-27 12:57:47 +0000131#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500132
133/*-----------------------------------------------------------------------
134 * FLASH organization
135 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
138# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
139# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
140# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500141#endif
142
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800143#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144# define CONFIG_SYS_MAX_NAND_DEVICE 1
145# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
146# define CONFIG_SYS_NAND_SIZE 1
147# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500148# define NAND_ALLOW_ERASE_ALL 1
149# define CONFIG_JFFS2_NAND 1
150# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaedd3d72007-08-15 15:39:17 -0500152# define CONFIG_JFFS2_PART_OFFSET 0x00000000
TsiChungLiewec8468f2007-08-05 04:31:18 -0500153#endif
154
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liewf6afe722007-06-18 13:50:13 -0500156
157/* Configuration for environment
158 * Environment is embedded in u-boot in the second sector of the flash
159 */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500160
angelo@sysam.it6312a952015-03-29 22:54:16 +0200161#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -0600162 . = DEFINED(env_offset) ? env_offset : .; \
163 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +0200164
TsiChung Liewf6afe722007-06-18 13:50:13 -0500165/*-----------------------------------------------------------------------
166 * Cache Configuration
167 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liewf6afe722007-06-18 13:50:13 -0500169
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600170#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200171 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600172#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200173 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600174#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
175#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
176 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
177 CF_ACR_EN | CF_ACR_SM_ALL)
178#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
179 CF_CACR_DCM_P)
180
TsiChung Liewf6afe722007-06-18 13:50:13 -0500181/*-----------------------------------------------------------------------
182 * Chipselect bank definitions
183 */
184/*
185 * CS0 - NOR Flash 1, 2, 4, or 8MB
186 * CS1 - CompactFlash and registers
187 * CS2 - NAND Flash 16, 32, or 64MB
188 * CS3 - Available
189 * CS4 - Available
190 * CS5 - Available
191 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_CS0_BASE 0
193#define CONFIG_SYS_CS0_MASK 0x007f0001
194#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_CS1_BASE 0x10000000
197#define CONFIG_SYS_CS1_MASK 0x001f0001
198#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChung Liewf6afe722007-06-18 13:50:13 -0500199
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800200#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_CS2_BASE 0x20000000
stany MARCEL5ac9ea62011-10-19 00:17:13 +0800202#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChung Liewf6afe722007-06-18 13:50:13 -0500204#endif
205
TsiChung Liewf6afe722007-06-18 13:50:13 -0500206#endif /* _M5329EVB_H */