| TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000-2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #include <config.h> |
| 28 | #include <common.h> |
| 29 | #include <asm/io.h> |
| 30 | #include <asm/immap.h> |
| 31 | |
| 32 | DECLARE_GLOBAL_DATA_PTR; |
| 33 | |
| 34 | #if defined(CONFIG_CMD_NAND) |
| 35 | #include <nand.h> |
| 36 | #include <linux/mtd/mtd.h> |
| 37 | |
| 38 | #define SET_CLE 0x10 |
| 39 | #define CLR_CLE ~SET_CLE |
| 40 | #define SET_ALE 0x08 |
| 41 | #define CLR_ALE ~SET_ALE |
| 42 | |
| 43 | static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
| 44 | { |
| 45 | struct nand_chip *this = mtdinfo->priv; |
| 46 | volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; |
| 47 | u32 nand_baseaddr = (u32) this->IO_ADDR_W; |
| 48 | |
| 49 | switch (cmd) { |
| 50 | case NAND_CTL_SETNCE: |
| 51 | case NAND_CTL_CLRNCE: |
| 52 | break; |
| 53 | case NAND_CTL_SETCLE: |
| 54 | nand_baseaddr |= SET_CLE; |
| 55 | break; |
| 56 | case NAND_CTL_CLRCLE: |
| 57 | nand_baseaddr &= CLR_CLE; |
| 58 | break; |
| 59 | case NAND_CTL_SETALE: |
| 60 | nand_baseaddr |= SET_ALE; |
| 61 | break; |
| 62 | case NAND_CTL_CLRALE: |
| 63 | nand_baseaddr |= CLR_ALE; |
| 64 | break; |
| 65 | case NAND_CTL_SETWP: |
| 66 | fbcs->csmr2 |= FBCS_CSMR_WP; |
| 67 | break; |
| 68 | case NAND_CTL_CLRWP: |
| 69 | fbcs->csmr2 &= ~FBCS_CSMR_WP; |
| 70 | break; |
| 71 | } |
| 72 | this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); |
| 73 | } |
| 74 | |
| 75 | static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) |
| 76 | { |
| 77 | struct nand_chip *this = mtdinfo->priv; |
| 78 | *((volatile u8 *)(this->IO_ADDR_W)) = byte; |
| 79 | } |
| 80 | |
| 81 | static u8 nand_read_byte(struct mtd_info *mtdinfo) |
| 82 | { |
| 83 | struct nand_chip *this = mtdinfo->priv; |
| 84 | return (u8) (*((volatile u8 *)this->IO_ADDR_R)); |
| 85 | } |
| 86 | |
| 87 | static int nand_dev_ready(struct mtd_info *mtdinfo) |
| 88 | { |
| 89 | return 1; |
| 90 | } |
| 91 | |
| 92 | int board_nand_init(struct nand_chip *nand) |
| 93 | { |
| 94 | volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
| 95 | |
| 96 | *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; |
| 97 | |
| 98 | /* set up pin configuration */ |
| 99 | gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; |
| 100 | gpio->pddr_timer |= 0x08; |
| 101 | gpio->ppd_timer |= 0x08; |
| 102 | gpio->pclrr_timer = 0; |
| 103 | gpio->podr_timer = 0; |
| 104 | |
| 105 | nand->chip_delay = 50; |
| 106 | nand->eccmode = NAND_ECC_SOFT; |
| 107 | nand->hwcontrol = nand_hwcontrol; |
| 108 | nand->read_byte = nand_read_byte; |
| 109 | nand->write_byte = nand_write_byte; |
| 110 | nand->dev_ready = nand_dev_ready; |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | #endif |