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git01.mediatek.com / filogic / uboot / 20402064daf7a3c45d98ec411fd5dabe5dbcc3ee / . / arch / powerpc / dts / p3041ds.dts
blob: 069dae3b85b795ffdcd24357cb00cec193f6f603 [file] [log] [blame]
Hou Zhiqiangd9c6c602019-08-20 09:35:31 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P3041DS Device Tree Source
4 *
5 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
Madalin Bucurd394de52020-04-30 16:00:09 +0300[diff] [blame]6 * Copyright 2019-2020 NXP
Hou Zhiqiangd9c6c602019-08-20 09:35:31 +0000[diff] [blame]7 */
8
9/include/ "p3041.dtsi"
10
11/ {
12 model = "fsl,P3041DS";
13 compatible = "fsl,P3041DS";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
17
Madalin Bucurd394de52020-04-30 16:00:09 +0300[diff] [blame]18 aliases{
19 phy_rgmii_0 = &phy_rgmii_0;
20 phy_rgmii_1 = &phy_rgmii_1;
21 phy_sgmii_1c = &phy_sgmii_1c;
22 phy_sgmii_1d = &phy_sgmii_1d;
23 phy_sgmii_1e = &phy_sgmii_1e;
24 phy_sgmii_1f = &phy_sgmii_1f;
25 phy_xgmii_1 = &phy_xgmii_1;
26 phy_xgmii_2 = &phy_xgmii_2;
27 emi1_rgmii = &hydra_mdio_rgmii;
28 emi1_sgmii = &hydra_mdio_sgmii;
29 emi2_xgmii = &hydra_mdio_xgmii;
Xiaowei Bao7c4b1152020-09-21 12:26:07 +0530[diff] [blame]30 spi0 = &espi0;
Madalin Bucurd394de52020-04-30 16:00:09 +0300[diff] [blame]31 };
32
33 soc: soc@ffe000000 {
34 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
35 reg = <0xf 0xfe000000 0 0x00001000>;
36 fman@400000{
37 ethernet@e0000 {
38 phy-handle = <&phy_sgmii_1c>;
39 phy-connection-type = "sgmii";
40 };
41
42 ethernet@e2000 {
43 phy-handle = <&phy_sgmii_1d>;
44 phy-connection-type = "sgmii";
45 };
46
47 ethernet@e4000 {
48 phy-handle = <&phy_sgmii_1e>;
49 phy-connection-type = "sgmii";
50 };
51
52 ethernet@e6000 {
53 phy-handle = <&phy_sgmii_1f>;
54 phy-connection-type = "sgmii";
55 };
56
57 ethernet@e8000 {
58 phy-handle = <&phy_rgmii_1>;
59 phy-connection-type = "rgmii";
60 };
61
62 ethernet@f0000 {
63 phy-handle = <&phy_xgmii_1>;
64 phy-connection-type = "xgmii";
65 };
66
67 hydra_mdio_xgmii: mdio@f1000 {
68 status = "disabled";
69
70 phy_xgmii_1: ethernet-phy@4 {
71 compatible = "ethernet-phy-ieee802.3-c45";
72 reg = <0x4>;
73 };
74
75 phy_xgmii_2: ethernet-phy@0 {
76 compatible = "ethernet-phy-ieee802.3-c45";
77 reg = <0x0>;
78 };
79 };
80 };
81 };
82
83 lbc: localbus@ffe124000 {
84 reg = <0xf 0xfe124000 0 0x1000>;
85 ranges = <0 0 0xf 0xe8000000 0x08000000
86 2 0 0xf 0xffa00000 0x00040000
87 3 0 0xf 0xffdf0000 0x00008000>;
88
89 board-control@3,0 {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
93 reg = <3 0 0x30>;
94 ranges = <0 3 0 0x30>;
95
96 mdio-mux-emi1 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "mdio-mux-mmioreg", "mdio-mux";
100 mdio-parent-bus = <&mdio0>;
101 reg = <9 1>;
102 mux-mask = <0x78>;
103
104 hydra_mdio_rgmii: rgmii-mdio@8 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 reg = <8>;
108 status = "disabled";
109
110 phy_rgmii_0: ethernet-phy@0 {
111 reg = <0x0>;
112 };
113
114 phy_rgmii_1: ethernet-phy@1 {
115 reg = <0x1>;
116 };
117 };
118
119 hydra_mdio_sgmii: sgmii-mdio@28 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 reg = <0x28>;
123 status = "disabled";
124
125 phy_sgmii_1c: ethernet-phy@1c {
126 reg = <0x1c>;
127 };
128
129 phy_sgmii_1d: ethernet-phy@1d {
130 reg = <0x1d>;
131 };
132
133 phy_sgmii_1e: ethernet-phy@1e {
134 reg = <0x1e>;
135 };
136
137 phy_sgmii_1f: ethernet-phy@1f {
138 reg = <0x1f>;
139 };
140 };
141 };
142 };
143 };
Hou Zhiqiangd9c6c602019-08-20 09:35:31 +0000[diff] [blame]144};
Madalin Bucurd394de52020-04-30 16:00:09 +0300[diff] [blame]145
Xiaowei Bao7c4b1152020-09-21 12:26:07 +0530[diff] [blame]146&espi0 {
147 status = "okay";
148 flash@0 {
149 compatible = "jedec,spi-nor";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0>;
153 /* input clock */
154 spi-max-frequency = <10000000>;
155 };
156};
157
Madalin Bucurd394de52020-04-30 16:00:09 +0300[diff] [blame]158/include/ "p3041si-post.dtsi"