Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 9 | #include <asm/ppc440.h> |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 10 | #include <libfdt.h> |
| 11 | #include <fdt_support.h> |
Stefan Roese | 4947e5c | 2008-06-10 15:34:11 +0200 | [diff] [blame] | 12 | #include <i2c.h> |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 13 | #include <asm/processor.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <asm/mmu.h> |
| 16 | #include <asm/4xx_pcie.h> |
Stefan Roese | de21eab | 2010-09-16 14:30:37 +0200 | [diff] [blame] | 17 | #include <asm/ppc4xx-gpio.h> |
Stefan Roese | 14fd12f | 2009-10-02 14:35:16 +0200 | [diff] [blame] | 18 | #include <asm/errno.h> |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 19 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 20 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Stefan Roese | b97b4c4 | 2010-09-28 08:06:06 +0200 | [diff] [blame] | 24 | struct board_bcsr { |
| 25 | u8 board_id; |
| 26 | u8 cpld_rev; |
| 27 | u8 led_user; |
| 28 | u8 board_status; |
| 29 | u8 reset_ctrl; |
| 30 | u8 flash_ctrl; |
| 31 | u8 eth_ctrl; |
| 32 | u8 usb_ctrl; |
| 33 | u8 irq_ctrl; |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 34 | }; |
Stefan Roese | dfdd95e | 2008-03-28 14:09:04 +0100 | [diff] [blame] | 35 | |
| 36 | #define BOARD_CANYONLANDS_PCIE 1 |
| 37 | #define BOARD_CANYONLANDS_SATA 2 |
| 38 | #define BOARD_GLACIER 3 |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 39 | #define BOARD_ARCHES 4 |
| 40 | |
Stefan Roese | d8d63ba | 2009-07-27 10:53:43 +0200 | [diff] [blame] | 41 | /* |
Stefan Roese | 88fbf93 | 2010-04-15 16:07:28 +0200 | [diff] [blame] | 42 | * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with |
Stefan Roese | d8d63ba | 2009-07-27 10:53:43 +0200 | [diff] [blame] | 43 | * board specific values. |
| 44 | */ |
| 45 | #if defined(CONFIG_ARCHES) |
| 46 | u32 ddr_wrdtr(u32 default_val) { |
| 47 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823); |
| 48 | } |
| 49 | #else |
| 50 | u32 ddr_wrdtr(u32 default_val) { |
| 51 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); |
| 52 | } |
| 53 | |
| 54 | u32 ddr_clktr(u32 default_val) { |
| 55 | return (SDRAM_CLKTR_CLKP_90_DEG_ADV); |
| 56 | } |
| 57 | #endif |
| 58 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 59 | #if defined(CONFIG_ARCHES) |
| 60 | /* |
| 61 | * FPGA read/write helper macros |
| 62 | */ |
| 63 | static inline int board_fpga_read(int offset) |
| 64 | { |
| 65 | int data; |
| 66 | |
| 67 | data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset)); |
| 68 | |
| 69 | return data; |
| 70 | } |
| 71 | |
| 72 | static inline void board_fpga_write(int offset, int data) |
| 73 | { |
| 74 | out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data); |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * CPLD read/write helper macros |
| 79 | */ |
| 80 | static inline int board_cpld_read(int offset) |
| 81 | { |
| 82 | int data; |
| 83 | |
| 84 | out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); |
| 85 | data = in_8((void *)(CONFIG_SYS_CPLD_DATA)); |
| 86 | |
| 87 | return data; |
| 88 | } |
| 89 | |
| 90 | static inline void board_cpld_write(int offset, int data) |
| 91 | { |
| 92 | out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); |
| 93 | out_8((void *)(CONFIG_SYS_CPLD_DATA), data); |
| 94 | } |
Stefan Roese | 38ee94f | 2009-07-29 08:46:10 +0200 | [diff] [blame] | 95 | #else |
| 96 | static int pvr_460ex(void) |
| 97 | { |
| 98 | u32 pvr = get_pvr(); |
| 99 | |
| 100 | if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) || |
| 101 | (pvr == PVR_460EX_RB)) |
| 102 | return 1; |
| 103 | |
| 104 | return 0; |
| 105 | } |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 106 | #endif /* defined(CONFIG_ARCHES) */ |
Stefan Roese | dfdd95e | 2008-03-28 14:09:04 +0100 | [diff] [blame] | 107 | |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 108 | int board_early_init_f(void) |
| 109 | { |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 110 | #if !defined(CONFIG_ARCHES) |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 111 | u32 sdr0_cust0; |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 112 | struct board_bcsr *bcsr_data = |
| 113 | (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; |
| 114 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 115 | #endif |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 116 | |
Stefan Roese | b685b9c | 2008-04-02 08:39:33 +0200 | [diff] [blame] | 117 | /* |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 118 | * Setup the interrupt controller polarities, triggers, etc. |
Stefan Roese | b685b9c | 2008-04-02 08:39:33 +0200 | [diff] [blame] | 119 | */ |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 120 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
| 121 | mtdcr(UIC0ER, 0x00000000); /* disable all */ |
| 122 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ |
| 123 | mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ |
| 124 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ |
| 125 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ |
| 126 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 127 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 128 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
| 129 | mtdcr(UIC1ER, 0x00000000); /* disable all */ |
| 130 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ |
| 131 | mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ |
| 132 | mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ |
| 133 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ |
| 134 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 135 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 136 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
| 137 | mtdcr(UIC2ER, 0x00000000); /* disable all */ |
| 138 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ |
| 139 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ |
| 140 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ |
| 141 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ |
| 142 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 143 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 144 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
| 145 | mtdcr(UIC3ER, 0x00000000); /* disable all */ |
| 146 | mtdcr(UIC3CR, 0x00000000); /* all non-critical */ |
| 147 | mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ |
| 148 | mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ |
| 149 | mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ |
| 150 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 151 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 152 | #if !defined(CONFIG_ARCHES) |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 153 | /* SDR Setting - enable NDFC */ |
| 154 | mfsdr(SDR0_CUST0, sdr0_cust0); |
| 155 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
| 156 | SDR0_CUST0_NDFC_ENABLE | |
| 157 | SDR0_CUST0_NDFC_BW_8_BIT | |
| 158 | SDR0_CUST0_NDFC_ARE_MASK | |
| 159 | SDR0_CUST0_NDFC_BAC_ENCODE(3) | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 161 | mtsdr(SDR0_CUST0, sdr0_cust0); |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 162 | #endif |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 163 | |
| 164 | /* |
| 165 | * Configure PFC (Pin Function Control) registers |
| 166 | * UART0: 4 pins |
| 167 | */ |
| 168 | mtsdr(SDR0_PFC1, 0x00040000); |
| 169 | |
| 170 | /* Enable PCI host functionality in SDR0_PCI0 */ |
| 171 | mtsdr(SDR0_PCI0, 0xe0000000); |
| 172 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 173 | #if !defined(CONFIG_ARCHES) |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 174 | /* Enable ethernet and take out of reset */ |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 175 | out_8(&bcsr_data->eth_ctrl, 0) ; |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 176 | |
| 177 | /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 178 | out_8(&bcsr_data->flash_ctrl, 0) ; |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 179 | mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ |
| 180 | |
Stefan Roese | 8d0f6b2 | 2008-03-05 12:31:53 +0100 | [diff] [blame] | 181 | /* Setup PLB4-AHB bridge based on the system address map */ |
| 182 | mtdcr(AHB_TOP, 0x8000004B); |
| 183 | mtdcr(AHB_BOT, 0x8000004B); |
| 184 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 185 | #endif |
Stefan Roese | 8d0f6b2 | 2008-03-05 12:31:53 +0100 | [diff] [blame] | 186 | |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 187 | return 0; |
| 188 | } |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 189 | |
| 190 | #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) |
| 191 | int usb_board_init(void) |
| 192 | { |
| 193 | struct board_bcsr *bcsr_data = |
| 194 | (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; |
| 195 | u8 val; |
| 196 | |
| 197 | /* Enable USB host & USB-OTG */ |
| 198 | val = in_8(&bcsr_data->usb_ctrl); |
| 199 | val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); |
| 200 | out_8(&bcsr_data->usb_ctrl, val); |
| 201 | |
Rupjyoti Sarmah | 4010376 | 2010-10-01 14:31:28 +0530 | [diff] [blame] | 202 | /* |
| 203 | * Configure USB-STP pins as alternate and not GPIO |
| 204 | * It seems to be neccessary to configure the STP pins as GPIO |
| 205 | * input at powerup (perhaps while USB reset is asserted). So |
| 206 | * we configure those pins to their "real" function now. |
| 207 | */ |
| 208 | gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); |
| 209 | gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); |
| 210 | |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | int usb_board_stop(void) |
| 215 | { |
| 216 | struct board_bcsr *bcsr_data = |
| 217 | (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; |
| 218 | u8 val; |
| 219 | |
| 220 | /* Disable USB host & USB-OTG */ |
| 221 | val = in_8(&bcsr_data->usb_ctrl); |
| 222 | val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); |
| 223 | out_8(&bcsr_data->usb_ctrl, val); |
| 224 | |
Rupjyoti Sarmah | 4010376 | 2010-10-01 14:31:28 +0530 | [diff] [blame] | 225 | /* Reconfigure USB-STP pins as input */ |
| 226 | gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0); |
| 227 | gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0); |
| 228 | |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 229 | return 0; |
| 230 | } |
| 231 | |
| 232 | int usb_board_init_fail(void) |
| 233 | { |
| 234 | return usb_board_stop(); |
| 235 | } |
| 236 | #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 237 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 238 | #if !defined(CONFIG_ARCHES) |
Stefan Roese | b685b9c | 2008-04-02 08:39:33 +0200 | [diff] [blame] | 239 | static void canyonlands_sata_init(int board_type) |
| 240 | { |
| 241 | u32 reg; |
| 242 | |
| 243 | if (board_type == BOARD_CANYONLANDS_SATA) { |
| 244 | /* Put SATA in reset */ |
| 245 | SDR_WRITE(SDR0_SRST1, 0x00020001); |
| 246 | |
| 247 | /* Set the phy for SATA, not PCI-E port 0 */ |
| 248 | reg = SDR_READ(PESDR0_PHY_CTL_RST); |
| 249 | SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001); |
| 250 | reg = SDR_READ(PESDR0_L0CLK); |
| 251 | SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007); |
| 252 | SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111); |
| 253 | SDR_WRITE(PESDR0_L0DRV, 0x00000104); |
| 254 | |
| 255 | /* Bring SATA out of reset */ |
| 256 | SDR_WRITE(SDR0_SRST1, 0x00000000); |
| 257 | } |
| 258 | } |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 259 | #endif /* !defined(CONFIG_ARCHES) */ |
| 260 | |
| 261 | int get_cpu_num(void) |
| 262 | { |
| 263 | int cpu = NA_OR_UNKNOWN_CPU; |
| 264 | |
| 265 | #if defined(CONFIG_ARCHES) |
| 266 | int cpu_num; |
| 267 | |
| 268 | cpu_num = board_fpga_read(0x3); |
| 269 | |
| 270 | /* sanity check; assume cpu numbering starts and increments from 0 */ |
| 271 | if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) |
| 272 | cpu = cpu_num; |
| 273 | #endif |
| 274 | |
| 275 | return cpu; |
| 276 | } |
Stefan Roese | b685b9c | 2008-04-02 08:39:33 +0200 | [diff] [blame] | 277 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 278 | #if !defined(CONFIG_ARCHES) |
Stefan Roese | b685b9c | 2008-04-02 08:39:33 +0200 | [diff] [blame] | 279 | int checkboard(void) |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 280 | { |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 281 | struct board_bcsr *bcsr_data = |
| 282 | (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 283 | char buf[64]; |
| 284 | int i = getenv_f("serial#", buf, sizeof(buf)); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 285 | |
Stefan Roese | 38ee94f | 2009-07-29 08:46:10 +0200 | [diff] [blame] | 286 | if (pvr_460ex()) { |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 287 | printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 288 | if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE) |
Stefan Roese | dfdd95e | 2008-03-28 14:09:04 +0100 | [diff] [blame] | 289 | gd->board_type = BOARD_CANYONLANDS_PCIE; |
| 290 | else |
| 291 | gd->board_type = BOARD_CANYONLANDS_SATA; |
Stefan Roese | 38ee94f | 2009-07-29 08:46:10 +0200 | [diff] [blame] | 292 | } else { |
| 293 | printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); |
| 294 | gd->board_type = BOARD_GLACIER; |
Stefan Roese | dfdd95e | 2008-03-28 14:09:04 +0100 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | switch (gd->board_type) { |
| 298 | case BOARD_CANYONLANDS_PCIE: |
| 299 | case BOARD_GLACIER: |
| 300 | puts(", 2*PCIe"); |
| 301 | break; |
| 302 | |
| 303 | case BOARD_CANYONLANDS_SATA: |
| 304 | puts(", 1*PCIe/1*SATA"); |
| 305 | break; |
| 306 | } |
| 307 | |
Rupjyoti Sarmah | 4e23bff | 2010-07-07 18:14:48 +0530 | [diff] [blame] | 308 | printf(", Rev. %X", in_8(&bcsr_data->cpld_rev)); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 309 | |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 310 | if (i > 0) { |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 311 | puts(", serial# "); |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 312 | puts(buf); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 313 | } |
| 314 | putc('\n'); |
| 315 | |
Stefan Roese | b685b9c | 2008-04-02 08:39:33 +0200 | [diff] [blame] | 316 | canyonlands_sata_init(gd->board_type); |
| 317 | |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 318 | return (0); |
| 319 | } |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 320 | |
| 321 | #else /* defined(CONFIG_ARCHES) */ |
| 322 | |
| 323 | int checkboard(void) |
| 324 | { |
| 325 | char *s = getenv("serial#"); |
| 326 | |
| 327 | printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); |
| 328 | printf(" Revision %02x.%02x ", |
| 329 | board_fpga_read(0x0), board_fpga_read(0x1)); |
| 330 | |
| 331 | gd->board_type = BOARD_ARCHES; |
| 332 | |
| 333 | /* Only CPU0 has access to CPLD registers */ |
| 334 | if (get_cpu_num() == 0) { |
| 335 | u8 cfg_sw = board_cpld_read(0x1); |
| 336 | printf("(FPGA=%02x, CPLD=%02x)\n", |
| 337 | board_fpga_read(0x2), board_cpld_read(0x0)); |
| 338 | printf(" Configuration Switch %d%d%d%d\n", |
| 339 | ((cfg_sw >> 3) & 0x01), |
| 340 | ((cfg_sw >> 2) & 0x01), |
| 341 | ((cfg_sw >> 1) & 0x01), |
| 342 | ((cfg_sw >> 0) & 0x01)); |
| 343 | } else |
| 344 | printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); |
| 345 | |
| 346 | |
| 347 | if (s != NULL) |
| 348 | printf(" Serial# %s\n", s); |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | #endif /* !defined(CONFIG_ARCHES) */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 353 | |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 354 | #if defined(CONFIG_PCI) |
Stefan Roese | e53b5cd | 2009-10-29 15:04:35 +0100 | [diff] [blame] | 355 | int board_pcie_first(void) |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 356 | { |
Stefan Roese | dfdd95e | 2008-03-28 14:09:04 +0100 | [diff] [blame] | 357 | /* |
| 358 | * Canyonlands with SATA enabled has only one PCIe slot |
| 359 | * (2nd one). |
| 360 | */ |
| 361 | if (gd->board_type == BOARD_CANYONLANDS_SATA) |
Stefan Roese | e53b5cd | 2009-10-29 15:04:35 +0100 | [diff] [blame] | 362 | return 1; |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 363 | |
Stefan Roese | e53b5cd | 2009-10-29 15:04:35 +0100 | [diff] [blame] | 364 | return 0; |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 365 | } |
| 366 | #endif /* CONFIG_PCI */ |
| 367 | |
| 368 | int board_early_init_r (void) |
| 369 | { |
| 370 | /* |
| 371 | * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the |
| 372 | * boot EBC mapping only supports a maximum of 16MBytes |
| 373 | * (4.ff00.0000 - 4.ffff.ffff). |
| 374 | * To solve this problem, the FLASH has to get remapped to another |
| 375 | * EBC address which accepts bigger regions: |
| 376 | * |
| 377 | * 0xfc00.0000 -> 4.cc00.0000 |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 378 | */ |
| 379 | |
| 380 | /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ |
Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame] | 381 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 382 | mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); |
Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame] | 383 | #else |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 384 | mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); |
Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame] | 385 | #endif |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 386 | |
| 387 | /* Remove TLB entry of boot EBC mapping */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 388 | remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 389 | |
| 390 | /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 391 | program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 392 | TLB_WORD2_I_ENABLE); |
| 393 | |
| 394 | /* |
| 395 | * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address |
| 396 | * 0xfc00.0000 is possible |
| 397 | */ |
Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame] | 398 | |
| 399 | /* |
| 400 | * Clear potential errors resulting from auto-calibration. |
| 401 | * If not done, then we could get an interrupt later on when |
| 402 | * exceptions are enabled. |
| 403 | */ |
| 404 | set_mcsr(get_mcsr()); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 405 | |
| 406 | return 0; |
| 407 | } |
| 408 | |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 409 | #if !defined(CONFIG_ARCHES) |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 410 | int misc_init_r(void) |
| 411 | { |
| 412 | u32 sdr0_srst1 = 0; |
| 413 | u32 eth_cfg; |
Stefan Roese | 4947e5c | 2008-06-10 15:34:11 +0200 | [diff] [blame] | 414 | u8 val; |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 415 | |
| 416 | /* |
| 417 | * Set EMAC mode/configuration (GMII, SGMII, RGMII...). |
| 418 | * This is board specific, so let's do it here. |
| 419 | */ |
| 420 | mfsdr(SDR0_ETH_CFG, eth_cfg); |
| 421 | /* disable SGMII mode */ |
| 422 | eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | |
| 423 | SDR0_ETH_CFG_SGMII1_ENABLE | |
| 424 | SDR0_ETH_CFG_SGMII0_ENABLE); |
| 425 | /* Set the for 2 RGMII mode */ |
| 426 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ |
| 427 | eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; |
Stefan Roese | 38ee94f | 2009-07-29 08:46:10 +0200 | [diff] [blame] | 428 | if (pvr_460ex()) |
Stefan Roese | 52df419 | 2008-03-19 16:20:49 +0100 | [diff] [blame] | 429 | eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; |
| 430 | else |
| 431 | eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 432 | mtsdr(SDR0_ETH_CFG, eth_cfg); |
| 433 | |
| 434 | /* |
| 435 | * The AHB Bridge core is held in reset after power-on or reset |
| 436 | * so enable it now |
| 437 | */ |
| 438 | mfsdr(SDR0_SRST1, sdr0_srst1); |
| 439 | sdr0_srst1 &= ~SDR0_SRST1_AHB; |
| 440 | mtsdr(SDR0_SRST1, sdr0_srst1); |
| 441 | |
Stefan Roese | 4947e5c | 2008-06-10 15:34:11 +0200 | [diff] [blame] | 442 | /* |
| 443 | * RTC/M41T62: |
| 444 | * Disable square wave output: Batterie will be drained |
| 445 | * quickly, when this output is not disabled |
| 446 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 447 | val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa); |
Stefan Roese | 4947e5c | 2008-06-10 15:34:11 +0200 | [diff] [blame] | 448 | val &= ~0x40; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 449 | i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val); |
Stefan Roese | 4947e5c | 2008-06-10 15:34:11 +0200 | [diff] [blame] | 450 | |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 451 | return 0; |
| 452 | } |
Adam Graham | 4900ed2 | 2008-10-08 10:12:53 -0700 | [diff] [blame] | 453 | |
| 454 | #else /* defined(CONFIG_ARCHES) */ |
| 455 | |
| 456 | int misc_init_r(void) |
| 457 | { |
| 458 | u32 eth_cfg = 0; |
| 459 | u32 eth_pll; |
| 460 | u32 reg; |
| 461 | |
| 462 | /* |
| 463 | * Set EMAC mode/configuration (GMII, SGMII, RGMII...). |
| 464 | * This is board specific, so let's do it here. |
| 465 | */ |
| 466 | |
| 467 | /* enable SGMII mode */ |
| 468 | eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | |
| 469 | SDR0_ETH_CFG_SGMII1_ENABLE | |
| 470 | SDR0_ETH_CFG_SGMII2_ENABLE); |
| 471 | |
| 472 | /* Set EMAC for MDIO */ |
| 473 | eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; |
| 474 | |
| 475 | /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ |
| 476 | eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); |
| 477 | |
| 478 | mtsdr(SDR0_ETH_CFG, eth_cfg); |
| 479 | |
| 480 | /* reset all SGMII interfaces */ |
| 481 | mfsdr(SDR0_SRST1, reg); |
| 482 | reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); |
| 483 | mtsdr(SDR0_SRST1, reg); |
| 484 | mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); |
| 485 | mtsdr(SDR0_SRST1, 0x00000000); |
| 486 | |
| 487 | do { |
| 488 | mfsdr(SDR0_ETH_PLL, eth_pll); |
| 489 | } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK)); |
| 490 | |
| 491 | return 0; |
| 492 | } |
| 493 | #endif /* !defined(CONFIG_ARCHES) */ |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 494 | |
| 495 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
Felix Radensky | fadfe70 | 2009-06-22 15:30:42 +0300 | [diff] [blame] | 496 | extern void __ft_board_setup(void *blob, bd_t *bd); |
| 497 | |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 498 | void ft_board_setup(void *blob, bd_t *bd) |
| 499 | { |
Felix Radensky | fadfe70 | 2009-06-22 15:30:42 +0300 | [diff] [blame] | 500 | __ft_board_setup(blob, bd); |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 501 | |
Stefan Roese | 7d2c2a5 | 2008-05-19 07:14:38 +0200 | [diff] [blame] | 502 | if (gd->board_type == BOARD_CANYONLANDS_SATA) { |
| 503 | /* |
| 504 | * When SATA is selected we need to disable the first PCIe |
| 505 | * node in the device tree, so that Linux doesn't initialize |
| 506 | * it. |
| 507 | */ |
Stefan Roese | c91600a | 2008-09-22 16:10:43 +0200 | [diff] [blame] | 508 | fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", |
| 509 | "disabled", sizeof("disabled"), 1); |
Stefan Roese | 7d2c2a5 | 2008-05-19 07:14:38 +0200 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | if (gd->board_type == BOARD_CANYONLANDS_PCIE) { |
| 513 | /* |
| 514 | * When PCIe is selected we need to disable the SATA |
| 515 | * node in the device tree, so that Linux doesn't initialize |
| 516 | * it. |
| 517 | */ |
Stefan Roese | c91600a | 2008-09-22 16:10:43 +0200 | [diff] [blame] | 518 | fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", |
| 519 | "disabled", sizeof("disabled"), 1); |
Stefan Roese | 7d2c2a5 | 2008-05-19 07:14:38 +0200 | [diff] [blame] | 520 | } |
Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 521 | } |
| 522 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |