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Sergey Kubushyne8f39122007-08-10 20:26:18 +02001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
4 * Based on:
5 *
6 * -------------------------------------------------------------------------
7 *
8 * linux/include/asm-arm/arch-davinci/hardware.h
9 *
10 * Copyright (C) 2006 Texas Instruments.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 */
33#ifndef __ASM_ARCH_HARDWARE_H
34#define __ASM_ARCH_HARDWARE_H
35
36#include <config.h>
37#include <asm/sizes.h>
38
39#define REG(addr) (*(volatile unsigned int *)(addr))
40#define REG_P(addr) ((volatile unsigned int *)(addr))
41
42typedef volatile unsigned int dv_reg;
43typedef volatile unsigned int * dv_reg_p;
44
45/*
46 * Base register addresses
47 */
48#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
49#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
50#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
51#define DAVINCI_UART0_BASE (0x01c20000)
52#define DAVINCI_UART1_BASE (0x01c20400)
53#define DAVINCI_UART2_BASE (0x01c20800)
54#define DAVINCI_I2C_BASE (0x01c21000)
55#define DAVINCI_TIMER0_BASE (0x01c21400)
56#define DAVINCI_TIMER1_BASE (0x01c21800)
57#define DAVINCI_WDOG_BASE (0x01c21c00)
58#define DAVINCI_PWM0_BASE (0x01c22000)
59#define DAVINCI_PWM1_BASE (0x01c22400)
60#define DAVINCI_PWM2_BASE (0x01c22800)
61#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
62#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
63#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
64#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
65#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000)
66#define DAVINCI_ARM_INTC_BASE (0x01c48000)
67#define DAVINCI_IEEE1394_BASE (0x01c60000)
68#define DAVINCI_USB_OTG_BASE (0x01c64000)
69#define DAVINCI_CFC_ATA_BASE (0x01c66000)
70#define DAVINCI_SPI_BASE (0x01c66800)
71#define DAVINCI_GPIO_BASE (0x01c67000)
72#define DAVINCI_UHPI_BASE (0x01c67800)
73#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
74#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000)
75#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000)
76#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000)
77#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000)
78#define DAVINCI_IMCOP_BASE (0x01cc0000)
79#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000)
80#define DAVINCI_VLYNQ_BASE (0x01e01000)
81#define DAVINCI_MCBSP_BASE (0x01e02000)
82#define DAVINCI_MMC_SD_BASE (0x01e10000)
83#define DAVINCI_MS_BASE (0x01e20000)
84#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
85#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
86#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
87#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
88#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000)
89
90/* Power and Sleep Controller (PSC) Domains */
91#define DAVINCI_GPSC_ARMDOMAIN 0
92#define DAVINCI_GPSC_DSPDOMAIN 1
93
94#define DAVINCI_LPSC_VPSSMSTR 0
95#define DAVINCI_LPSC_VPSSSLV 1
96#define DAVINCI_LPSC_TPCC 2
97#define DAVINCI_LPSC_TPTC0 3
98#define DAVINCI_LPSC_TPTC1 4
99#define DAVINCI_LPSC_EMAC 5
100#define DAVINCI_LPSC_EMAC_WRAPPER 6
101#define DAVINCI_LPSC_MDIO 7
102#define DAVINCI_LPSC_IEEE1394 8
103#define DAVINCI_LPSC_USB 9
104#define DAVINCI_LPSC_ATA 10
105#define DAVINCI_LPSC_VLYNQ 11
106#define DAVINCI_LPSC_UHPI 12
107#define DAVINCI_LPSC_DDR_EMIF 13
108#define DAVINCI_LPSC_AEMIF 14
109#define DAVINCI_LPSC_MMC_SD 15
110#define DAVINCI_LPSC_MEMSTICK 16
111#define DAVINCI_LPSC_McBSP 17
112#define DAVINCI_LPSC_I2C 18
113#define DAVINCI_LPSC_UART0 19
114#define DAVINCI_LPSC_UART1 20
115#define DAVINCI_LPSC_UART2 21
116#define DAVINCI_LPSC_SPI 22
117#define DAVINCI_LPSC_PWM0 23
118#define DAVINCI_LPSC_PWM1 24
119#define DAVINCI_LPSC_PWM2 25
120#define DAVINCI_LPSC_GPIO 26
121#define DAVINCI_LPSC_TIMER0 27
122#define DAVINCI_LPSC_TIMER1 28
123#define DAVINCI_LPSC_TIMER2 29
124#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
125#define DAVINCI_LPSC_ARM 31
126#define DAVINCI_LPSC_SCR2 32
127#define DAVINCI_LPSC_SCR3 33
128#define DAVINCI_LPSC_SCR4 34
129#define DAVINCI_LPSC_CROSSBAR 35
130#define DAVINCI_LPSC_CFG27 36
131#define DAVINCI_LPSC_CFG3 37
132#define DAVINCI_LPSC_CFG5 38
133#define DAVINCI_LPSC_GEM 39
134#define DAVINCI_LPSC_IMCOP 40
135
136/* Some PSC defines */
137#define PSC_CHP_SHRTSW (0x01c40038)
138#define PSC_GBLCTL (0x01c41010)
139#define PSC_EPCPR (0x01c41070)
140#define PSC_EPCCR (0x01c41078)
141#define PSC_PTCMD (0x01c41120)
142#define PSC_PTSTAT (0x01c41128)
143#define PSC_PDSTAT (0x01c41200)
144#define PSC_PDSTAT1 (0x01c41204)
145#define PSC_PDCTL (0x01c41300)
146#define PSC_PDCTL1 (0x01c41304)
147
148#define PSC_MDCTL_BASE (0x01c41a00)
149#define PSC_MDSTAT_BASE (0x01c41800)
150
151#define VDD3P3V_PWDN (0x01c40048)
152#define UART0_PWREMU_MGMT (0x01c20030)
153
154#define PSC_SILVER_BULLET (0x01c41a20)
155
156/* Some PLL defines */
157#define PLL1_PLLM (0x01c40910)
158#define PLL2_PLLM (0x01c40d10)
159#define PLL2_DIV2 (0x01c40d1c)
160
161/* Miscellania... */
162#define VBPR (0x20000020)
163#define PINMUX0 (0x01c40000)
164#define PINMUX1 (0x01c40004)
165
166#endif /* __ASM_ARCH_HARDWARE_H */