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wdenkefee1702002-07-20 20:14:13 +00001/*
2 * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307USA
21 */
22
wdenkefee1702002-07-20 20:14:13 +000023#include <config.h>
24#include <command.h>
25#include <74xx_7xx.h>
26#include <version.h>
27
28#include <ppc_asm.tmpl>
29#include <ppc_defs.h>
30
31#include <asm/cache.h>
32#include <asm/mmu.h>
33
Jon Loeligera5217742007-07-09 18:57:22 -050034#if defined(CONFIG_CMD_KGDB)
wdenkefee1702002-07-20 20:14:13 +000035
36 /*
37 * cache flushing routines for kgdb
38 */
39
40 .globl kgdb_flush_cache_all
41kgdb_flush_cache_all:
wdenk99651602004-09-28 21:39:45 +000042 lis r3,0
43 addis r4,r0,0x0040
44kgdb_flush_loop:
45 lwz r5,0(r3)
46 addi r3,r3,CFG_CACHELINE_SIZE
47 cmp 0,0,r3,r4
48 bne kgdb_flush_loop
wdenkefee1702002-07-20 20:14:13 +000049 SYNC
wdenk99651602004-09-28 21:39:45 +000050 mfspr r3,1008
51 ori r3,r3,0x8800
52 mtspr 1008,r3
53 sync
wdenkefee1702002-07-20 20:14:13 +000054 blr
55
56 .globl kgdb_flush_cache_range
57kgdb_flush_cache_range:
58 li r5,CFG_CACHELINE_SIZE-1
59 andc r3,r3,r5
60 subf r4,r3,r4
61 add r4,r4,r5
62 srwi. r4,r4,CFG_CACHELINE_SHIFT
63 beqlr
64 mtctr r4
65 mr r6,r3
661: dcbst 0,r3
67 addi r3,r3,CFG_CACHELINE_SIZE
68 bdnz 1b
69 sync /* wait for dcbst's to get to ram */
70 mtctr r4
712: icbi 0,r6
72 addi r6,r6,CFG_CACHELINE_SIZE
73 bdnz 2b
74 SYNC
75 blr
76
Jon Loeliger07efe2a2007-07-10 10:27:39 -050077#endif