blob: 15276e89d0195150bc2e1b8e9b65ee96f2a7d5ca [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
3 *
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
wdenk336b2bc2005-04-02 23:52:25 +00006 * board/cradle/lowlevel_init.S for another PXA250 setup that is
wdenkfe8c2802002-11-03 00:38:21 +00007 * much cleaner.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <version.h>
30#include <asm/arch/pxa-regs.h>
31
32DRAM_SIZE: .long CFG_DRAM_SIZE
33
34/* wait for coprocessor write complete */
35 .macro CPWAIT reg
36 mrc p15,0,\reg,c2,c0,0
37 mov \reg,\reg
38 sub pc,pc,#4
39 .endm
40
41
wdenkb666c8f2003-03-06 00:58:30 +000042/*
43 * Memory setup
44 */
45
wdenk336b2bc2005-04-02 23:52:25 +000046.globl lowlevel_init
47lowlevel_init:
wdenkfe8c2802002-11-03 00:38:21 +000048
49 mov r10, lr
50
wdenkb666c8f2003-03-06 00:58:30 +000051 /* Set up GPIO pins first ----------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +000052
53 ldr r0, =GPSR0
54 ldr r1, =CFG_GPSR0_VAL
55 str r1, [r0]
56
57 ldr r0, =GPSR1
58 ldr r1, =CFG_GPSR1_VAL
59 str r1, [r0]
60
61 ldr r0, =GPSR2
62 ldr r1, =CFG_GPSR2_VAL
63 str r1, [r0]
64
65 ldr r0, =GPCR0
66 ldr r1, =CFG_GPCR0_VAL
67 str r1, [r0]
68
69 ldr r0, =GPCR1
70 ldr r1, =CFG_GPCR1_VAL
71 str r1, [r0]
72
73 ldr r0, =GPCR2
74 ldr r1, =CFG_GPCR2_VAL
75 str r1, [r0]
76
77 ldr r0, =GPDR0
78 ldr r1, =CFG_GPDR0_VAL
79 str r1, [r0]
80
81 ldr r0, =GPDR1
82 ldr r1, =CFG_GPDR1_VAL
83 str r1, [r0]
84
85 ldr r0, =GPDR2
86 ldr r1, =CFG_GPDR2_VAL
87 str r1, [r0]
88
89 ldr r0, =GAFR0_L
90 ldr r1, =CFG_GAFR0_L_VAL
91 str r1, [r0]
92
93 ldr r0, =GAFR0_U
94 ldr r1, =CFG_GAFR0_U_VAL
95 str r1, [r0]
96
97 ldr r0, =GAFR1_L
98 ldr r1, =CFG_GAFR1_L_VAL
99 str r1, [r0]
100
101 ldr r0, =GAFR1_U
102 ldr r1, =CFG_GAFR1_U_VAL
103 str r1, [r0]
104
105 ldr r0, =GAFR2_L
106 ldr r1, =CFG_GAFR2_L_VAL
107 str r1, [r0]
108
109 ldr r0, =GAFR2_U
110 ldr r1, =CFG_GAFR2_U_VAL
111 str r1, [r0]
112
wdenkb666c8f2003-03-06 00:58:30 +0000113 ldr r0, =PSSR /* enable GPIO pins */
wdenkfe8c2802002-11-03 00:38:21 +0000114 ldr r1, =CFG_PSSR_VAL
115 str r1, [r0]
116
wdenkb666c8f2003-03-06 00:58:30 +0000117 /* ---------------------------------------------------------------- */
118 /* Enable memory interface */
119 /* */
120 /* The sequence below is based on the recommended init steps */
121 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
122 /* Chapter 10. */
123 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000124
wdenkb666c8f2003-03-06 00:58:30 +0000125 /* ---------------------------------------------------------------- */
126 /* Step 1: Wait for at least 200 microsedonds to allow internal */
127 /* clocks to settle. Only necessary after hard reset... */
128 /* FIXME: can be optimized later */
129 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000130
wdenkb666c8f2003-03-06 00:58:30 +0000131 ldr r3, =OSCR /* reset the OS Timer Count to zero */
wdenkfe8c2802002-11-03 00:38:21 +0000132 mov r2, #0
133 str r2, [r3]
wdenkb666c8f2003-03-06 00:58:30 +0000134 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
135 /* so 0x300 should be plenty */
wdenkfe8c2802002-11-03 00:38:21 +00001361:
137 ldr r2, [r3]
138 cmp r4, r2
139 bgt 1b
140
141mem_init:
wdenkb666c8f2003-03-06 00:58:30 +0000142
wdenk57b2d802003-06-27 21:31:46 +0000143 ldr r1, =MEMC_BASE /* get memory controller base addr. */
wdenkb666c8f2003-03-06 00:58:30 +0000144
145 /* ---------------------------------------------------------------- */
146 /* Step 2a: Initialize Asynchronous static memory controller */
147 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000148
wdenkb666c8f2003-03-06 00:58:30 +0000149 /* MSC registers: timing, bus width, mem type */
wdenkfe8c2802002-11-03 00:38:21 +0000150
wdenk57b2d802003-06-27 21:31:46 +0000151 /* MSC0: nCS(0,1) */
152 ldr r2, =CFG_MSC0_VAL
153 str r2, [r1, #MSC0_OFFSET]
154 ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
wdenkb666c8f2003-03-06 00:58:30 +0000155 /* that data latches */
wdenk57b2d802003-06-27 21:31:46 +0000156 /* MSC1: nCS(2,3) */
157 ldr r2, =CFG_MSC1_VAL
158 str r2, [r1, #MSC1_OFFSET]
159 ldr r2, [r1, #MSC1_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000160
wdenkb666c8f2003-03-06 00:58:30 +0000161 /* MSC2: nCS(4,5) */
wdenk57b2d802003-06-27 21:31:46 +0000162 ldr r2, =CFG_MSC2_VAL
163 str r2, [r1, #MSC2_OFFSET]
164 ldr r2, [r1, #MSC2_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000165
wdenkb666c8f2003-03-06 00:58:30 +0000166 /* ---------------------------------------------------------------- */
167 /* Step 2b: Initialize Card Interface */
168 /* ---------------------------------------------------------------- */
169
170 /* MECR: Memory Expansion Card Register */
wdenk57b2d802003-06-27 21:31:46 +0000171 ldr r2, =CFG_MECR_VAL
172 str r2, [r1, #MECR_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000173 ldr r2, [r1, #MECR_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000174
wdenkb666c8f2003-03-06 00:58:30 +0000175 /* MCMEM0: Card Interface slot 0 timing */
wdenk57b2d802003-06-27 21:31:46 +0000176 ldr r2, =CFG_MCMEM0_VAL
177 str r2, [r1, #MCMEM0_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000178 ldr r2, [r1, #MCMEM0_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000179
wdenk57b2d802003-06-27 21:31:46 +0000180 /* MCMEM1: Card Interface slot 1 timing */
181 ldr r2, =CFG_MCMEM1_VAL
182 str r2, [r1, #MCMEM1_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000183 ldr r2, [r1, #MCMEM1_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000184
wdenkb666c8f2003-03-06 00:58:30 +0000185 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
wdenk57b2d802003-06-27 21:31:46 +0000186 ldr r2, =CFG_MCATT0_VAL
187 str r2, [r1, #MCATT0_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000188 ldr r2, [r1, #MCATT0_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000189
wdenkb666c8f2003-03-06 00:58:30 +0000190 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
wdenk57b2d802003-06-27 21:31:46 +0000191 ldr r2, =CFG_MCATT1_VAL
192 str r2, [r1, #MCATT1_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000193 ldr r2, [r1, #MCATT1_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000194
wdenkb666c8f2003-03-06 00:58:30 +0000195 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
wdenk57b2d802003-06-27 21:31:46 +0000196 ldr r2, =CFG_MCIO0_VAL
197 str r2, [r1, #MCIO0_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000198 ldr r2, [r1, #MCIO0_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000199
wdenkb666c8f2003-03-06 00:58:30 +0000200 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
wdenk57b2d802003-06-27 21:31:46 +0000201 ldr r2, =CFG_MCIO1_VAL
202 str r2, [r1, #MCIO1_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000203 ldr r2, [r1, #MCIO1_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000204
wdenkb666c8f2003-03-06 00:58:30 +0000205 /* ---------------------------------------------------------------- */
wdenk57b2d802003-06-27 21:31:46 +0000206 /* Step 2c: Write FLYCNFG FIXME: what's that??? */
207 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000208
wdenkfe8c2802002-11-03 00:38:21 +0000209
wdenkb666c8f2003-03-06 00:58:30 +0000210 /* ---------------------------------------------------------------- */
wdenk57b2d802003-06-27 21:31:46 +0000211 /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
212 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000213
wdenkb666c8f2003-03-06 00:58:30 +0000214 /* Before accessing MDREFR we need a valid DRI field, so we set */
215 /* this to power on defaults + DRI field. */
wdenkfe8c2802002-11-03 00:38:21 +0000216
wdenk57b2d802003-06-27 21:31:46 +0000217 ldr r3, =CFG_MDREFR_VAL
218 ldr r2, =0xFFF
219 and r3, r3, r2
wdenkb666c8f2003-03-06 00:58:30 +0000220 ldr r4, =0x03ca4000
wdenk57b2d802003-06-27 21:31:46 +0000221 orr r4, r4, r3
wdenkb666c8f2003-03-06 00:58:30 +0000222 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
wdenk57b2d802003-06-27 21:31:46 +0000223 ldr r4, [r1, #MDREFR_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000224
wdenk57b2d802003-06-27 21:31:46 +0000225 /* Note: preserve the mdrefr value in r4 */
wdenkfe8c2802002-11-03 00:38:21 +0000226
wdenkfe8c2802002-11-03 00:38:21 +0000227
wdenkb666c8f2003-03-06 00:58:30 +0000228 /* ---------------------------------------------------------------- */
229 /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
230 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000231
wdenkb666c8f2003-03-06 00:58:30 +0000232 /* Initialize SXCNFG register. Assert the enable bits */
wdenkfe8c2802002-11-03 00:38:21 +0000233
wdenkb666c8f2003-03-06 00:58:30 +0000234 /* Write SXMRS to cause an MRS command to all enabled banks of */
235 /* synchronous static memory. Note that SXLCR need not be written */
236 /* at this time. */
wdenkfe8c2802002-11-03 00:38:21 +0000237
wdenkb666c8f2003-03-06 00:58:30 +0000238 /* FIXME: we use async mode for now */
wdenkfe8c2802002-11-03 00:38:21 +0000239
wdenkfe8c2802002-11-03 00:38:21 +0000240
wdenk57b2d802003-06-27 21:31:46 +0000241 /* ---------------------------------------------------------------- */
242 /* Step 4: Initialize SDRAM */
243 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000244
wdenk57b2d802003-06-27 21:31:46 +0000245 /* set MDREFR according to user define with exception of a few bits */
wdenkfe8c2802002-11-03 00:38:21 +0000246
wdenk57b2d802003-06-27 21:31:46 +0000247 ldr r4, =CFG_MDREFR_VAL
wdenkb666c8f2003-03-06 00:58:30 +0000248 orr r4, r4, #(MDREFR_SLFRSH)
249 bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
250 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
wdenk57b2d802003-06-27 21:31:46 +0000251 ldr r4, [r1, #MDREFR_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000252
wdenkb666c8f2003-03-06 00:58:30 +0000253 /* Step 4b: de-assert MDREFR:SLFRSH. */
wdenkfe8c2802002-11-03 00:38:21 +0000254
wdenkb666c8f2003-03-06 00:58:30 +0000255 bic r4, r4, #(MDREFR_SLFRSH)
wdenk57b2d802003-06-27 21:31:46 +0000256 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
257 ldr r4, [r1, #MDREFR_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000258
259
wdenkb666c8f2003-03-06 00:58:30 +0000260 /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
wdenkfe8c2802002-11-03 00:38:21 +0000261
wdenk57b2d802003-06-27 21:31:46 +0000262 ldr r4, =CFG_MDREFR_VAL
263 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
264 ldr r4, [r1, #MDREFR_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000265
wdenkfe8c2802002-11-03 00:38:21 +0000266
wdenkb666c8f2003-03-06 00:58:30 +0000267 /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
268 /* configure but not enable each SDRAM partition pair. */
wdenkfe8c2802002-11-03 00:38:21 +0000269
wdenkb666c8f2003-03-06 00:58:30 +0000270 ldr r4, =CFG_MDCNFG_VAL
271 bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
wdenkfe8c2802002-11-03 00:38:21 +0000272
wdenk57b2d802003-06-27 21:31:46 +0000273 str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
274 ldr r4, [r1, #MDCNFG_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000275
wdenkfe8c2802002-11-03 00:38:21 +0000276
wdenkb666c8f2003-03-06 00:58:30 +0000277 /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
278 /* 100..200 µsec. */
279
280 ldr r3, =OSCR /* reset the OS Timer Count to zero */
wdenk57b2d802003-06-27 21:31:46 +0000281 mov r2, #0
wdenkfe8c2802002-11-03 00:38:21 +0000282 str r2, [r3]
wdenkb666c8f2003-03-06 00:58:30 +0000283 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
284 /* so 0x300 should be plenty */
wdenkfe8c2802002-11-03 00:38:21 +00002851:
286 ldr r2, [r3]
287 cmp r4, r2
288 bgt 1b
289
290
wdenkb666c8f2003-03-06 00:58:30 +0000291 /* Step 4f: Trigger a number (usually 8) refresh cycles by */
292 /* attempting non-burst read or write accesses to disabled */
293 /* SDRAM, as commonly specified in the power up sequence */
294 /* documented in SDRAM data sheets. The address(es) used */
295 /* for this purpose must not be cacheable. */
wdenkfe8c2802002-11-03 00:38:21 +0000296
wdenkb666c8f2003-03-06 00:58:30 +0000297 ldr r3, =CFG_DRAM_BASE
298 str r2, [r3]
299 str r2, [r3]
300 str r2, [r3]
301 str r2, [r3]
302 str r2, [r3]
303 str r2, [r3]
304 str r2, [r3]
305 str r2, [r3]
wdenkfe8c2802002-11-03 00:38:21 +0000306
wdenkfe8c2802002-11-03 00:38:21 +0000307
wdenkb666c8f2003-03-06 00:58:30 +0000308 /* Step 4g: Write MDCNFG with enable bits asserted */
309 /* (MDCNFG:DEx set to 1). */
wdenkfe8c2802002-11-03 00:38:21 +0000310
wdenk57b2d802003-06-27 21:31:46 +0000311 ldr r3, [r1, #MDCNFG_OFFSET]
wdenkb666c8f2003-03-06 00:58:30 +0000312 orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
wdenk57b2d802003-06-27 21:31:46 +0000313 str r3, [r1, #MDCNFG_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000314
wdenkb666c8f2003-03-06 00:58:30 +0000315 /* Step 4h: Write MDMRS. */
wdenkfe8c2802002-11-03 00:38:21 +0000316
wdenk57b2d802003-06-27 21:31:46 +0000317 ldr r2, =CFG_MDMRS_VAL
318 str r2, [r1, #MDMRS_OFFSET]
wdenkfe8c2802002-11-03 00:38:21 +0000319
320
wdenkb666c8f2003-03-06 00:58:30 +0000321 /* We are finished with Intel's memory controller initialisation */
wdenkfe8c2802002-11-03 00:38:21 +0000322
wdenkfe8c2802002-11-03 00:38:21 +0000323
wdenkb666c8f2003-03-06 00:58:30 +0000324 /* ---------------------------------------------------------------- */
325 /* Disable (mask) all interrupts at interrupt controller */
326 /* ---------------------------------------------------------------- */
327
328initirqs:
329
wdenk57b2d802003-06-27 21:31:46 +0000330 mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
331 ldr r2, =ICLR
332 str r1, [r2]
wdenkfe8c2802002-11-03 00:38:21 +0000333
wdenk57b2d802003-06-27 21:31:46 +0000334 ldr r2, =ICMR /* mask all interrupts at the controller */
335 str r1, [r2]
wdenkfe8c2802002-11-03 00:38:21 +0000336
337
wdenk57b2d802003-06-27 21:31:46 +0000338 /* ---------------------------------------------------------------- */
wdenkb666c8f2003-03-06 00:58:30 +0000339 /* Clock initialisation */
wdenk57b2d802003-06-27 21:31:46 +0000340 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000341
wdenkb666c8f2003-03-06 00:58:30 +0000342initclks:
343
344 /* Disable the peripheral clocks, and set the core clock frequency */
345 /* (hard-coding at 398.12MHz for now). */
346
347 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
348 /* Note: See label 'ENABLECLKS' for the re-enabling */
wdenk57b2d802003-06-27 21:31:46 +0000349 ldr r1, =CKEN
350 mov r2, #0
351 str r2, [r1]
wdenkfe8c2802002-11-03 00:38:21 +0000352
353
wdenk57b2d802003-06-27 21:31:46 +0000354 /* default value in case no valid rotary switch setting is found */
355 ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
wdenkfe8c2802002-11-03 00:38:21 +0000356
wdenk57b2d802003-06-27 21:31:46 +0000357 /* ... and write the core clock config register */
358 ldr r1, =CCCR
359 str r2, [r1]
wdenkfe8c2802002-11-03 00:38:21 +0000360
wdenkb666c8f2003-03-06 00:58:30 +0000361#ifdef RTC
362 /* enable the 32Khz oscillator for RTC and PowerManager */
363
wdenk57b2d802003-06-27 21:31:46 +0000364 ldr r1, =OSCC
365 mov r2, #OSCC_OON
366 str r2, [r1]
wdenkfe8c2802002-11-03 00:38:21 +0000367
wdenkb666c8f2003-03-06 00:58:30 +0000368 /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
369 /* has settled. */
wdenkfe8c2802002-11-03 00:38:21 +000037060:
wdenk57b2d802003-06-27 21:31:46 +0000371 ldr r2, [r1]
372 ands r2, r2, #1
373 beq 60b
wdenkb666c8f2003-03-06 00:58:30 +0000374#endif
wdenkfe8c2802002-11-03 00:38:21 +0000375
wdenkb666c8f2003-03-06 00:58:30 +0000376 /* ---------------------------------------------------------------- */
377 /* */
wdenk57b2d802003-06-27 21:31:46 +0000378 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000379
380 /* Save SDRAM size */
381 ldr r1, =DRAM_SIZE
382 str r8, [r1]
383
wdenkb666c8f2003-03-06 00:58:30 +0000384 /* Interrupt init: Mask all interrupts */
wdenkfe8c2802002-11-03 00:38:21 +0000385 ldr r0, =ICMR /* enable no sources */
386 mov r1, #0
387 str r1, [r0]
388
wdenkb666c8f2003-03-06 00:58:30 +0000389 /* FIXME */
390
wdenkfe8c2802002-11-03 00:38:21 +0000391#define NODEBUG
392#ifdef NODEBUG
393 /*Disable software and data breakpoints */
394 mov r0,#0
395 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
396 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
397 mcr p15,0,r0,c14,c4,0 /* dbcon */
398
399 /*Enable all debug functionality */
400 mov r0,#0x80000000
401 mcr p14,0,r0,c10,c0,0 /* dcsr */
402
403#endif
404
wdenk57b2d802003-06-27 21:31:46 +0000405 /* ---------------------------------------------------------------- */
wdenk336b2bc2005-04-02 23:52:25 +0000406 /* End lowlevel_init */
wdenk57b2d802003-06-27 21:31:46 +0000407 /* ---------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +0000408
wdenk336b2bc2005-04-02 23:52:25 +0000409endlowlevel_init:
wdenkfe8c2802002-11-03 00:38:21 +0000410
411 mov pc, lr