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Suman Anna3b431102022-05-25 13:38:47 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board specific initialization for AM62x platforms
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 *
8 */
9
Nikhil M Jain155a0822023-01-31 15:35:19 +053010#include <env.h>
Suman Anna3b431102022-05-25 13:38:47 +053011#include <spl.h>
Nikhil M Jain155a0822023-01-31 15:35:19 +053012#include <video.h>
13#include <splash.h>
Georgi Vlaev18c0fbf2022-06-14 17:45:33 +030014#include <k3-ddrss.h>
Suman Anna3b431102022-05-25 13:38:47 +053015#include <fdt_support.h>
Nikhil M Jain155a0822023-01-31 15:35:19 +053016#include <asm/io.h>
Suman Anna3b431102022-05-25 13:38:47 +053017#include <asm/arch/hardware.h>
Nikhil M Jain155a0822023-01-31 15:35:19 +053018#include <dm/uclass.h>
Suman Anna3b431102022-05-25 13:38:47 +053019
20DECLARE_GLOBAL_DATA_PTR;
21
Nikhil M Jain155a0822023-01-31 15:35:19 +053022#ifdef CONFIG_SPLASH_SCREEN
23static struct splash_location default_splash_locations[] = {
24 {
25 .name = "mmc",
26 .storage = SPLASH_STORAGE_MMC,
27 .flags = SPLASH_STORAGE_FS,
28 .devpart = "1:1",
29 },
30};
31
32int splash_screen_prepare(void)
33{
34 return splash_source_load(default_splash_locations,
35 ARRAY_SIZE(default_splash_locations));
36}
37#endif
38
Suman Anna3b431102022-05-25 13:38:47 +053039int board_init(void)
40{
41 return 0;
42}
43
44int dram_init(void)
45{
Georgi Vlaev8a9ceb42022-06-14 17:45:32 +030046 return fdtdec_setup_mem_size_base();
Suman Anna3b431102022-05-25 13:38:47 +053047}
48
49int dram_init_banksize(void)
50{
Georgi Vlaev8a9ceb42022-06-14 17:45:32 +030051 return fdtdec_setup_memory_banksize();
Suman Anna3b431102022-05-25 13:38:47 +053052}
Georgi Vlaev18c0fbf2022-06-14 17:45:33 +030053
54#if defined(CONFIG_SPL_BUILD)
55#if defined(CONFIG_K3_AM64_DDRSS)
56static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
57{
58 struct udevice *dev;
59 int ret;
60
61 dram_init_banksize();
62
63 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
64 if (ret)
65 panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
66
67 ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
68 if (ret)
69 printf("Error fixing up ddr node for ECC use! %d\n", ret);
70}
71#else
72static void fixup_memory_node(struct spl_image_info *spl_image)
73{
74 u64 start[CONFIG_NR_DRAM_BANKS];
75 u64 size[CONFIG_NR_DRAM_BANKS];
76 int bank;
77 int ret;
78
79 dram_init();
80 dram_init_banksize();
81
82 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
83 start[bank] = gd->bd->bi_dram[bank].start;
84 size[bank] = gd->bd->bi_dram[bank].size;
85 }
86
87 /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
88 ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
89 CONFIG_NR_DRAM_BANKS);
90 if (ret)
91 printf("Error fixing up memory node! %d\n", ret);
92}
93#endif
94
95void spl_perform_fixups(struct spl_image_info *spl_image)
96{
97#if defined(CONFIG_K3_AM64_DDRSS)
98 fixup_ddr_driver_for_ecc(spl_image);
99#else
100 fixup_memory_node(spl_image);
101#endif
102}
103#endif