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Dirk Eibach81b37932011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach81b37932011-01-21 09:31:21 +01006 */
7
8#include <common.h>
9#include <command.h>
10#include <asm/processor.h>
11#include <asm/io.h>
12#include <asm/ppc4xx-gpio.h>
Dirk Eibach6b4b92f2012-04-26 03:54:23 +000013#include <dtt.h>
Dirk Eibach81b37932011-01-21 09:31:21 +010014
Dirk Eibach9a659572012-04-26 03:54:22 +000015#include "405ep.h"
Dirk Eibach81b37932011-01-21 09:31:21 +010016#include <gdsys_fpga.h>
17
18#include "../common/osd.h"
19
Dirk Eibach9a659572012-04-26 03:54:22 +000020#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
Dirk Eibachcf868222011-04-06 13:53:44 +020022#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
Dirk Eibacha46eb6e2011-04-06 13:53:46 +020023#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
24
Dirk Eibach9a659572012-04-26 03:54:22 +000025#define LATCH2_MC2_PRESENT_N 0x0080
26
Dirk Eibach81b37932011-01-21 09:31:21 +010027enum {
Dirk Eibachfbb4e532015-10-28 11:46:28 +010028 UNITTYPE_MAIN = 1<<0,
29 UNITTYPE_SERVER = 1<<1,
30 UNITTYPE_DISPLAYPORT = 1<<2,
Dirk Eibach81b37932011-01-21 09:31:21 +010031};
32
33enum {
34 HWVER_101 = 0,
35 HWVER_110 = 1,
Dirk Eibachfbb4e532015-10-28 11:46:28 +010036 HWVER_130 = 2,
37 HWVER_140 = 3,
38 HWVER_150 = 4,
39 HWVER_160 = 5,
40 HWVER_170 = 6,
Dirk Eibach81b37932011-01-21 09:31:21 +010041};
42
43enum {
44 AUDIO_NONE = 0,
45 AUDIO_TX = 1,
46 AUDIO_RX = 2,
47 AUDIO_RXTX = 3,
48};
49
50enum {
51 SYSCLK_156250 = 2,
52};
53
54enum {
55 RAM_NONE = 0,
56 RAM_DDR2_32 = 1,
57 RAM_DDR2_64 = 2,
58};
59
Dirk Eibach20614a22013-06-26 16:04:26 +020060struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
61
Dirk Eibach6b4b92f2012-04-26 03:54:23 +000062int misc_init_r(void)
63{
64 /* startup fans */
65 dtt_init();
66
67 return 0;
68}
69
Dirk Eibacha46eb6e2011-04-06 13:53:46 +020070static unsigned int get_hwver(void)
71{
72 u16 latch3 = in_le16((void *)LATCH3_BASE);
73
74 return latch3 & 0x0003;
75}
76
77static unsigned int get_mc2_present(void)
78{
79 u16 latch2 = in_le16((void *)LATCH2_BASE);
80
81 return !(latch2 & LATCH2_MC2_PRESENT_N);
82}
83
Dirk Eibach81b37932011-01-21 09:31:21 +010084static void print_fpga_info(unsigned dev)
85{
Dirk Eibach20614a22013-06-26 16:04:26 +020086 u16 versions;
87 u16 fpga_version;
88 u16 fpga_features;
Dirk Eibach81b37932011-01-21 09:31:21 +010089 unsigned unit_type;
90 unsigned hardware_version;
Dirk Eibach81b37932011-01-21 09:31:21 +010091 unsigned feature_rs232;
92 unsigned feature_audio;
93 unsigned feature_sysclock;
94 unsigned feature_ramconfig;
95 unsigned feature_carrier_speed;
96 unsigned feature_carriers;
97 unsigned feature_video_channels;
98 int fpga_state = get_fpga_state(dev);
99
100 printf("FPGA%d: ", dev);
101
Dirk Eibach20614a22013-06-26 16:04:26 +0200102 FPGA_GET_REG(dev, versions, &versions);
103 FPGA_GET_REG(dev, fpga_version, &fpga_version);
104 FPGA_GET_REG(dev, fpga_features, &fpga_features);
105
Dirk Eibach81b37932011-01-21 09:31:21 +0100106 hardware_version = versions & 0x000f;
107
108 if (fpga_state
109 && !((hardware_version == HWVER_101)
110 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
111 puts("not available\n");
Tom Rini98003f82016-07-15 15:51:40 -0400112 if (fpga_state & FPGA_STATE_DONE_FAILED)
113 puts(" Waiting for FPGA-DONE timed out.\n");
114 if (fpga_state & FPGA_STATE_REFLECTION_FAILED)
115 puts(" FPGA reflection test failed.\n");
Dirk Eibach81b37932011-01-21 09:31:21 +0100116 return;
117 }
118
119 unit_type = (versions >> 4) & 0x000f;
120 hardware_version = versions & 0x000f;
Dirk Eibach81b37932011-01-21 09:31:21 +0100121 feature_rs232 = fpga_features & (1<<11);
122 feature_audio = (fpga_features >> 9) & 0x0003;
123 feature_sysclock = (fpga_features >> 7) & 0x0003;
124 feature_ramconfig = (fpga_features >> 5) & 0x0003;
125 feature_carrier_speed = fpga_features & (1<<4);
126 feature_carriers = (fpga_features >> 2) & 0x0003;
127 feature_video_channels = fpga_features & 0x0003;
128
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100129 if (unit_type & UNITTYPE_MAIN)
130 printf("Mainchannel ");
131 else
132 printf("Videochannel ");
Dirk Eibach81b37932011-01-21 09:31:21 +0100133
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100134 if (unit_type & UNITTYPE_SERVER)
135 printf("Serverside ");
136 else
137 printf("Userside ");
Dirk Eibach81b37932011-01-21 09:31:21 +0100138
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100139 if (unit_type & UNITTYPE_DISPLAYPORT)
140 printf("DisplayPort");
141 else
142 printf("DVI-DL");
143
144 switch (hardware_version) {
145 case HWVER_101:
146 printf(" HW-Ver 1.01\n");
Dirk Eibach81b37932011-01-21 09:31:21 +0100147 break;
148
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100149 case HWVER_110:
150 printf(" HW-Ver 1.10-1.20\n");
Dirk Eibach81b37932011-01-21 09:31:21 +0100151 break;
152
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100153 case HWVER_130:
154 printf(" HW-Ver 1.30\n");
Dirk Eibach81b37932011-01-21 09:31:21 +0100155 break;
Dirk Eibach81b37932011-01-21 09:31:21 +0100156
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100157 case HWVER_140:
158 printf(" HW-Ver 1.40-1.43\n");
Dirk Eibach81b37932011-01-21 09:31:21 +0100159 break;
160
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100161 case HWVER_150:
162 printf(" HW-Ver 1.50\n");
Dirk Eibach50477bf2012-04-26 03:54:24 +0000163 break;
164
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100165 case HWVER_160:
166 printf(" HW-Ver 1.60-1.61\n");
Dirk Eibach50477bf2012-04-26 03:54:24 +0000167 break;
168
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100169 case HWVER_170:
170 printf(" HW-Ver 1.70\n");
Dirk Eibach81b37932011-01-21 09:31:21 +0100171 break;
172
173 default:
174 printf(" HW-Ver %d(not supported)\n",
175 hardware_version);
176 break;
177 }
178
179 printf(" FPGA V %d.%02d, features:",
180 fpga_version / 100, fpga_version % 100);
181
182 printf(" %sRS232", feature_rs232 ? "" : "no ");
183
184 switch (feature_audio) {
185 case AUDIO_NONE:
186 printf(", no audio");
187 break;
188
189 case AUDIO_TX:
190 printf(", audio tx");
191 break;
192
193 case AUDIO_RX:
194 printf(", audio rx");
195 break;
196
197 case AUDIO_RXTX:
198 printf(", audio rx+tx");
199 break;
200
201 default:
202 printf(", audio %d(not supported)", feature_audio);
203 break;
204 }
205
206 switch (feature_sysclock) {
207 case SYSCLK_156250:
208 printf(", clock 156.25 MHz");
209 break;
210
211 default:
212 printf(", clock %d(not supported)", feature_sysclock);
213 break;
214 }
215
216 puts(",\n ");
217
218 switch (feature_ramconfig) {
219 case RAM_NONE:
220 printf("no RAM");
221 break;
222
223 case RAM_DDR2_32:
224 printf("RAM 32 bit DDR2");
225 break;
226
227 case RAM_DDR2_64:
228 printf("RAM 64 bit DDR2");
229 break;
230
231 default:
232 printf("RAM %d(not supported)", feature_ramconfig);
233 break;
234 }
235
236 printf(", %d carrier(s) %s", feature_carriers,
237 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
238
239 printf(", %d video channel(s)\n", feature_video_channels);
240}
241
242/*
243 * Check Board Identity:
244 */
245int checkboard(void)
246{
Dirk Eibach6b4b92f2012-04-26 03:54:23 +0000247 char *s = getenv("serial#");
Dirk Eibach81b37932011-01-21 09:31:21 +0100248
Dirk Eibach6b4b92f2012-04-26 03:54:23 +0000249 puts("Board: ");
Dirk Eibach81b37932011-01-21 09:31:21 +0100250
Dirk Eibach6b4b92f2012-04-26 03:54:23 +0000251 puts("DLVision 10G");
Dirk Eibach81b37932011-01-21 09:31:21 +0100252
Dirk Eibach6b4b92f2012-04-26 03:54:23 +0000253 if (s != NULL) {
Dirk Eibach81b37932011-01-21 09:31:21 +0100254 puts(", serial# ");
Dirk Eibach6b4b92f2012-04-26 03:54:23 +0000255 puts(s);
Dirk Eibach81b37932011-01-21 09:31:21 +0100256 }
257
258 puts("\n");
259
Dirk Eibach81b37932011-01-21 09:31:21 +0100260 return 0;
261}
262
263int last_stage_init(void)
264{
Dirk Eibach20614a22013-06-26 16:04:26 +0200265 u16 versions;
266
267 FPGA_GET_REG(0, versions, &versions);
Dirk Eibachcf868222011-04-06 13:53:44 +0200268
Dirk Eibach6b4b92f2012-04-26 03:54:23 +0000269 print_fpga_info(0);
270 if (get_mc2_present())
271 print_fpga_info(1);
272
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100273 if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
Dirk Eibachcf868222011-04-06 13:53:44 +0200274 return 0;
275
Dirk Eibacha46eb6e2011-04-06 13:53:46 +0200276 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
Dirk Eibachcf868222011-04-06 13:53:44 +0200277 osd_probe(0);
Dirk Eibach81b37932011-01-21 09:31:21 +0100278
Dirk Eibacha46eb6e2011-04-06 13:53:46 +0200279 if (get_mc2_present() &&
280 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
Dirk Eibachcf868222011-04-06 13:53:44 +0200281 osd_probe(1);
Dirk Eibach81b37932011-01-21 09:31:21 +0100282
283 return 0;
284}
Dirk Eibach9a659572012-04-26 03:54:22 +0000285
286void gd405ep_init(void)
287{
288}
289
290void gd405ep_set_fpga_reset(unsigned state)
291{
292 if (state) {
293 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
294 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
295 } else {
296 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
297 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
298 }
299}
300
301void gd405ep_setup_hw(void)
302{
303 /*
304 * set "startup-finished"-gpios
305 */
306 gpio_write_bit(21, 0);
307 gpio_write_bit(22, 1);
308}
309
310int gd405ep_get_fpga_done(unsigned fpga)
311{
312 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
313}