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git01.mediatek.com / filogic / uboot / 1f5a510b6878e737ffd997eb8ea38e8a257cf417 / . / arch / arm / dts / vf610-colibri-eval-v3-u-boot.dtsi
blob: 572d40877ef985f0870dd1704a91112593669283 [file] [log] [blame]
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2019-2022 Toradex
4 */
5
6/ {
7 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]8 bootph-all;
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]9 };
10};
11
12&aips0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-all;
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]14};
15
16&dcu0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-all;
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]18};
19
20&iomuxc {
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_ddr>;
23
24 pinctrl_ddr: ddrgrp {
25 fsl,pins = <
26 VF610_PAD_DDR_A15__DDR_A_15 0x180
27 VF610_PAD_DDR_A14__DDR_A_14 0x180
28 VF610_PAD_DDR_A13__DDR_A_13 0x180
29 VF610_PAD_DDR_A12__DDR_A_12 0x180
30 VF610_PAD_DDR_A11__DDR_A_11 0x180
31 VF610_PAD_DDR_A10__DDR_A_10 0x180
32 VF610_PAD_DDR_A9__DDR_A_9 0x180
33 VF610_PAD_DDR_A8__DDR_A_8 0x180
34 VF610_PAD_DDR_A7__DDR_A_7 0x180
35 VF610_PAD_DDR_A6__DDR_A_6 0x180
36 VF610_PAD_DDR_A5__DDR_A_5 0x180
37 VF610_PAD_DDR_A4__DDR_A_4 0x180
38 VF610_PAD_DDR_A3__DDR_A_3 0x180
39 VF610_PAD_DDR_A2__DDR_A_2 0x180
40 VF610_PAD_DDR_A1__DDR_A_1 0x180
41 VF610_PAD_DDR_A0__DDR_A_0 0x180
42 VF610_PAD_DDR_BA2__DDR_BA_2 0x180
43 VF610_PAD_DDR_BA1__DDR_BA_1 0x180
44 VF610_PAD_DDR_BA0__DDR_BA_0 0x180
45 VF610_PAD_DDR_CAS__DDR_CAS_B 0x180
46 VF610_PAD_DDR_CKE__DDR_CKE_0 0x180
47 VF610_PAD_DDR_CLK__DDR_CLK_0 0x180
48 VF610_PAD_DDR_CS__DDR_CS_B_0 0x180
49 VF610_PAD_DDR_D15__DDR_D_15 0x10180
50 VF610_PAD_DDR_D14__DDR_D_14 0x10180
51 VF610_PAD_DDR_D13__DDR_D_13 0x10180
52 VF610_PAD_DDR_D12__DDR_D_12 0x10180
53 VF610_PAD_DDR_D11__DDR_D_11 0x10180
54 VF610_PAD_DDR_D10__DDR_D_10 0x10180
55 VF610_PAD_DDR_D9__DDR_D_9 0x10180
56 VF610_PAD_DDR_D8__DDR_D_8 0x10180
57 VF610_PAD_DDR_D7__DDR_D_7 0x10180
58 VF610_PAD_DDR_D6__DDR_D_6 0x10180
59 VF610_PAD_DDR_D5__DDR_D_5 0x10180
60 VF610_PAD_DDR_D4__DDR_D_4 0x10180
61 VF610_PAD_DDR_D3__DDR_D_3 0x10180
62 VF610_PAD_DDR_D2__DDR_D_2 0x10180
63 VF610_PAD_DDR_D1__DDR_D_1 0x10180
64 VF610_PAD_DDR_D0__DDR_D_0 0x10180
65 VF610_PAD_DDR_DQM1__DDR_DQM_1 0x10180
66 VF610_PAD_DDR_DQM0__DDR_DQM_0 0x10180
67 VF610_PAD_DDR_DQS1__DDR_DQS_1 0x10180
68 VF610_PAD_DDR_DQS0__DDR_DQS_0 0x10180
69 VF610_PAD_DDR_RAS__DDR_RAS_B 0x180
70 VF610_PAD_DDR_WE__DDR_WE_B 0x180
71 VF610_PAD_DDR_ODT1__DDR_ODT_0 0x180
72 VF610_PAD_DDR_ODT0__DDR_ODT_1 0x180
73 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x180
74 VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x180
75 VF610_PAD_DDR_RESETB 0x180
76 >;
77 };
78};
79
80&pinctrl_ddr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-all;
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]82};
83
84&pinctrl_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-all;
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]86};
87
88&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-all;
Marcel Ziswiler47fa5ff2022-07-21 15:27:38 +0200[diff] [blame]90};