blob: 1ced6190ab2b255715d2108693314819865c50b4 [file] [log] [blame]
Masahiro Yamada0bc56842018-04-16 12:35:33 +09001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier PXs3 Reference Board
4//
5// Copyright (C) 2017 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada47ff9d52017-01-21 18:05:30 +09007
8/dts-v1/;
Masahiro Yamada23bdb3d2017-08-29 12:20:53 +09009#include "uniphier-pxs3.dtsi"
10#include "uniphier-support-card.dtsi"
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090011
12/ {
13 model = "UniPhier PXs3 Reference Board";
14 compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
15
Masahiro Yamadace6ca3c2017-03-13 00:16:40 +090016 chosen {
17 stdout-path = "serial0:115200n8";
18 };
19
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090020 aliases {
21 serial0 = &serial0;
Masahiro Yamada5e8f4ad2020-08-04 14:41:09 +090022 serial1 = &serialsc;
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090023 serial2 = &serial2;
24 serial3 = &serial3;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 i2c6 = &i2c6;
Masahiro Yamada423471f2020-07-09 15:08:14 +090030 spi0 = &spi0;
31 spi1 = &spi1;
32 ethernet0 = &eth0;
33 ethernet1 = &eth1;
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090034 };
35
Masahiro Yamadace6ca3c2017-03-13 00:16:40 +090036 memory@80000000 {
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090037 device_type = "memory";
38 reg = <0 0x80000000 0 0xa0000000>;
39 };
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090040};
41
42&ethsc {
Kunihiko Hayashic13863f2023-02-28 11:37:09 +090043 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090044};
45
Masahiro Yamada5e8f4ad2020-08-04 14:41:09 +090046&serialsc {
Kunihiko Hayashic13863f2023-02-28 11:37:09 +090047 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
Masahiro Yamada5e8f4ad2020-08-04 14:41:09 +090048};
49
Masahiro Yamada423471f2020-07-09 15:08:14 +090050&spi0 {
51 status = "okay";
52};
53
54&spi1 {
55 status = "okay";
56};
57
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090058&serial0 {
59 status = "okay";
60};
61
Masahiro Yamadab61327d2018-03-15 11:43:03 +090062&serial2 {
63 status = "okay";
64};
65
66&serial3 {
67 status = "okay";
68};
69
Masahiro Yamada6c086d02017-11-25 00:25:35 +090070&gpio {
Kunihiko Hayashic13863f2023-02-28 11:37:09 +090071 xirq4-hog {
Masahiro Yamada6c086d02017-11-25 00:25:35 +090072 gpio-hog;
73 gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
74 input;
75 };
76};
77
Masahiro Yamada47ff9d52017-01-21 18:05:30 +090078&i2c0 {
79 status = "okay";
80};
Masahiro Yamada23bdb3d2017-08-29 12:20:53 +090081
82&i2c1 {
83 status = "okay";
84};
85
86&i2c2 {
87 status = "okay";
88};
89
90&i2c3 {
91 status = "okay";
92};
93
Masahiro Yamada008073b2018-06-19 16:11:47 +090094&sd {
95 status = "okay";
96};
97
Masahiro Yamada0bc56842018-04-16 12:35:33 +090098&eth0 {
99 status = "okay";
100 phy-handle = <&ethphy0>;
101};
102
103&mdio0 {
Masahiro Yamada5e8f4ad2020-08-04 14:41:09 +0900104 ethphy0: ethernet-phy@0 {
Masahiro Yamada0bc56842018-04-16 12:35:33 +0900105 reg = <0>;
106 };
107};
108
109&eth1 {
110 status = "okay";
111 phy-handle = <&ethphy1>;
112};
113
114&mdio1 {
Masahiro Yamada5e8f4ad2020-08-04 14:41:09 +0900115 ethphy1: ethernet-phy@0 {
Masahiro Yamada0bc56842018-04-16 12:35:33 +0900116 reg = <0>;
117 };
118};
119
Masahiro Yamada23bdb3d2017-08-29 12:20:53 +0900120&usb0 {
121 status = "okay";
122};
123
124&usb1 {
125 status = "okay";
126};
Masahiro Yamadaa0a95bb2017-10-17 21:19:43 +0900127
Masahiro Yamadac9026882019-04-12 18:55:50 +0900128&pcie {
129 status = "okay";
130};
131
Masahiro Yamadaa0a95bb2017-10-17 21:19:43 +0900132&nand {
133 status = "okay";
Kunihiko Hayashic13863f2023-02-28 11:37:09 +0900134
135 nand@0 {
136 reg = <0>;
137 };
138};
139
140&ahci0 {
141 status = "okay";
142};
143
144&ahci1 {
145 status = "okay";
Masahiro Yamadaa0a95bb2017-10-17 21:19:43 +0900146};
Masahiro Yamada423471f2020-07-09 15:08:14 +0900147
148&pinctrl_ether_rgmii {
149 tx {
150 pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
151 "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
152 drive-strength = <9>;
153 };
154};
155
156&pinctrl_ether1_rgmii {
157 tx {
158 pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
159 "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
160 drive-strength = <9>;
161 };
162};